Wafer backside interconnect structure connected to TSVs

• US 9,449,875 B2
• Filed: 07/03/2014
• Issued: 09/20/2016
• Est. Priority Date: 09/22/2009
• Status: Active Grant

• Current Assignee: Advanced Manufacturing Innovations Incorporated
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Ming-Fa, Chiou, Wen-Chih, Shue, Shau-Lin
• Primary Examiner(s): HO, HOANG QUAN TRAN
• Application Number:
  US14/323,677
• Publication Number:
  US 20140322909A1
• Time in Patent Office: 810 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76813 involving a partial via etch
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76841 Barrier, adhesion or liner layers
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05025 the internal layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05546 Dual damascene structure
• CPC Class Codes: H01L 2224/05547 comprising a core and a coating
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/13007 Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/14181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/811 : the bump connector being supplied to the parts to be connected in the bonding apparatus
• CPC Class Codes: H01L 2224/8136 : Bonding interfaces of the semiconductor or solid state body
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line.

Claims

1. A method for forming an integrated circuit structure, the method comprising:

providing a semiconductor substrate having an active semiconductor device formed on a first side of the semiconductor substrate;

forming a conductive via passing through the semiconductor substrate; and

forming a metal feature on a second side of the semiconductor substrate opposing the first side of the semiconductor substrate, the metal feature comprising;

a metal pad overlying the conductive via in a first dielectric layer, wherein the metal pad contacts the conductive via, and wherein the conductive via is at least partially disposed in the first dielectric layer; and

a metal line higher than the conductive via, relative the second side of the semiconductor substrate, wherein the metal line comprises a dual damascene structure.

2. The method of claim 1 further comprising forming a metal bump overlying the metal line relative the second side of the semiconductor substrate.

3. The method of claim 1, wherein forming the metal feature comprises forming the metal line in the first dielectric layer.

4. The method of claim 1, wherein forming the metal feature comprises:

forming the first dielectric layer over the semiconductor substrate relative the second side of the semiconductor substrate;

forming the metal pad in the first dielectric layer;

forming a second dielectric layer over the first dielectric layer relative the second side of the semiconductor substrate; and

forming the metal line in the second dielectric layer.

5. The method of claim 1, wherein forming the metal feature comprises forming a conductive barrier layer on sidewalls and a bottom surface of the metal pad relative the second side of the semiconductor substrate.

6. The method of claim 1, wherein forming the metal feature comprises:

patterning a via opening extending through in a dielectric layer;

patterning a trench opening in the dielectric layer, wherein the trench opening is connected to and has a greater horizontal dimension than the via opening, and wherein the trench opening does not extend through the dielectric layer; and

filling the via opening and the trench opening with a metal to form the metal line.

11. The method of claim 1, further comprising:

etching back the second side of the semiconductor substrate to expose sidewalls of a portion of the conductive via; and

forming the first dielectric layer over the second side of the semiconductor substrate, wherein the first dielectric layer extends along the sidewalls of the portion of the conductive via.

12. The method of claim 11, wherein forming the metal feature comprises:

patterning a pad opening in the first dielectric layer to expose the portion of the conductive via; and

forming the metal pad in the pad opening.

13. The method of claim 11 further comprising an isolation layer on a sidewall of the conductive via below a top surface of the portion of the conductive via.

14. The method of claim 1, wherein a bottom surface of a via portion of the metal line is substantially level with a bottom surface of the metal pad.

7. A method for forming an integrated circuit structure, the method comprising:

providing a semiconductor substrate having a front surface and a back surface opposite the front surface;

forming an active device at the front surface of the semiconductor substrate;

forming a conductive via extending at least partially through the semiconductor substrate;

etching back the back surface of the semiconductor substrate to expose a sidewall of the conductive via;

forming a dielectric layer over the back surface of the semiconductor substrate and along a sidewall of the conductive via;

forming a first metal feature in the dielectric layer and electrically connected to the conductive via, wherein the first metal feature extends past edges of the conductive via in all horizontal directions; and

forming a second metal feature over the semiconductor substrate relative the back surface, wherein the second metal feature comprises a dual damascene structure.

8. The method of claim 7, wherein the first metal feature is disposed in a dielectric layer, and wherein the method further comprises forming an etch stop layer between the dielectric layer and the semiconductor substrate.

9. The method of claim 7, wherein forming the second metal feature comprises forming the second metal feature in a same dielectric layer as the first metal feature.

10. The method of claim 7, wherein forming the second metal feature comprises forming the second metal feature in a different dielectric layer as the first metal feature.

15. A method comprising:

forming a conductive via extending through a semiconductor substrate;

etching the semiconductor substrate so that the conductive via extends above a first surface of the semiconductor substrate;

depositing a dielectric layer over the first surface of the semiconductor substrate, wherein the dielectric layer extends along a sidewall of the conductive via;

patterning the dielectric layer to define a pad opening extending through the dielectric layer and exposing the conductive via, wherein the pad opening is wider than the conductive via; and

forming a conductive pad in the pad opening.

16. The method of claim 15, wherein patterning the pad opening comprises exposing the sidewall of the conductive via, and wherein the conductive pad extends partially along the sidewall of the conductive via.

17. The method of claim 15 further comprising forming a conductive feature in the dielectric layer adjacent the conductive pad, wherein the conductive feature comprises a dual damascene structure.

18. The method of claim 15 further comprising a conductive feature in a second dielectric layer over the dielectric layer, wherein the conductive feature comprises a dual damascene structure.

19. The method of claim 15 further comprising:

forming an isolation layer on sidewalls of the conductive via; and

recessing the isolation layer below a top surface of the conductive via.