Method of forming replacement gate PFET having TiALCO layer for improved NBTI performance

• US 9,449,887 B2
• Filed: 12/08/2014
• Issued: 09/20/2016
• Est. Priority Date: 12/08/2014
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Kannan, Balaji, Ando, Takashi, Narayanan, Vijay
• Primary Examiner(s): Jung, Michael
• Application Number:
  US14/563,009
• Publication Number:
  US 20160163814A1
• Time in Patent Office: 652 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66606 with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology H01L29/66621 takes precedence
• CPC Class Codes: H01L 29/66871 Processes wherein the final gate is made after the formation of the source and drain regions in the active layer, e.g. dummy-gate processes

Abstract

A method of forming a transistor device includes forming an interfacial layer and a dielectric layer over a substrate; and forming a workfunction metal layer over the dielectric layer, the workfunction metal layer comprising a titanium-aluminum-carbon-oxygen (TiAlCO) layer.

Claims

1. A method comprising:

forming an interfacial layer and a dielectric layer over portions of a substrate corresponding to removed dummy gate structures;

forming a p-type field effect transistor (PFET) workfunction metal layer over the dielectric layer in a p-type field effect transistor (PFET) region of the substrate and in an n-type field effect transistor (NFET) region of the substrate, the workfunction metal layer comprising a titanium-aluminum-carbon-oxygen (TiAlCO) layer;

removing the TiAlCO layer from the NFET region of the substrate;

forming an NFET workfunction metal layer in the NFET region of the substrate; and

forming a gate metal layer over the PFET workfunction metal layer,

wherein the gate metal layer, the PFET workfunction metal layer, the dielectric layer, and the interfacial layer define a gate stack.

2. The method of claim 1, wherein the TiAlCO layer has an atomic concentration range of 10-20% for Ti, 10-20% for Al, 5-15% for C, and 45-75% for O.

3. The method of claim 1, wherein the workfunction metal layer is formed using atomic layer deposition (ALD).

4. The method of claim 1, wherein the TiAlCO layer is removed from the NFET region of the substrate by lithographical patterning.

5. The method of claim 4, further comprising:

forming a protective layer over the TiAlCO layer in the PFET region of the substrate.

6. The method of claim 5, wherein the protective layer is comprised of titanium nitride (TiN).

7. The method of claim 1, further comprising:

forming a protective layer over the TiAlCO layer in the PFET region of the substrate.

8. The method of claim 7, wherein the protective layer is comprised of titanium nitride (TiN).

9. The method of claim 1, further comprising:

forming a protective layer over the TiAlCO layer in the PFET region of the substrate and over the TiAlCO layer in the NFET region of the substrate; and

before the TiAlCO layer is removed from the NFET region of the substrate, removing the protective layer from the NFET region of the substrate.

10. The method of claim 9, wherein the protective layer is comprised of titanium nitride (TiN).