Chip package and method for forming the same
First Claim
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1. A chip package, comprising:
- a semiconductor substrate;
a device region formed in the semiconductor substrate;
at least one conducting pad disposed over a surface of the semiconductor substrate;
a protection substrate disposed over the surface of the semiconductor substrate;
a spacer layer disposed between the surface of the semiconductor substrate and the protection substrate, wherein the protection substrate and the spacer layer surround a cavity over the device region, the spacer layer has an outer side surface away from the cavity, and the outer side surface of the spacer layer is not a cutting surface;
a dielectric layer disposed between the surface of the semiconductor substrate and the spacer layer, wherein the dielectric layer covers the device region and the spacer layer is disposed over the dielectric layer; and
a portion of a sacrificial support layer disposed on the dielectric layer, wherein the portion of the sacrificial support layer is located between the spacer layer and a conducting pad of the at least one conducting pad which is closest to the spacer layer, and the portion of the sacrificial support layer is not in contact with the spacer layer.
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Abstract
An embodiment of the invention provides a chip package which includes: a semiconductor substrate; a device region formed in the semiconductor substrate; at least a conducting pad disposed over a surface of the semiconductor substrate; a protection plate disposed over the surface of the semiconductor substrate; and a spacer layer disposed between the surface of the semiconductor substrate and the protection plate, wherein the protection plate and the spacer layer surround a cavity over the device region, the spacer layer has an outer side surface away from the cavity, and the outer side surface of the spacer layer is not a cutting surface.
20 Citations
22 Claims
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1. A chip package, comprising:
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a semiconductor substrate; a device region formed in the semiconductor substrate; at least one conducting pad disposed over a surface of the semiconductor substrate; a protection substrate disposed over the surface of the semiconductor substrate; a spacer layer disposed between the surface of the semiconductor substrate and the protection substrate, wherein the protection substrate and the spacer layer surround a cavity over the device region, the spacer layer has an outer side surface away from the cavity, and the outer side surface of the spacer layer is not a cutting surface; a dielectric layer disposed between the surface of the semiconductor substrate and the spacer layer, wherein the dielectric layer covers the device region and the spacer layer is disposed over the dielectric layer; and a portion of a sacrificial support layer disposed on the dielectric layer, wherein the portion of the sacrificial support layer is located between the spacer layer and a conducting pad of the at least one conducting pad which is closest to the spacer layer, and the portion of the sacrificial support layer is not in contact with the spacer layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for forming a chip package, comprising:
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providing a semiconductor substrate, wherein at least one device region is formed in the semiconductor substrate, and at least one conducting pad is disposed over a surface of the semiconductor substrate; disposing a dielectric layer over the semiconductor substrate, wherein the dielectric layer covers the device region; providing a protection substrate; disposing a spacer layer over the surface of the dielectric layer or over the protection substrate; disposing a sacrificial support layer over the surface of the dielectric layer or over the protection substrate; disposing the protection substrate over the surface of the semiconductor substrate such that the protection substrate and the spacer layer surround a cavity over the at least one device region and the dielectric layer is disposed between the surface of the semiconductor substrate and the spacer layer; and dicing and removing a portion of the protection substrate and a portion of the sacrificial support layer to expose the at least one conducting pad, wherein the spacer layer has an outer side surface away from the cavity, and the outer side surface of the spacer layer is not a cutting surface, wherein the portion of the sacrificial support layer is located between the spacer layer and a conducting pad of the at least one conducting pad which is closest to the spacer layer, and the portion of the sacrificial support layer is not in contact with the spacer layer. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A chip package, comprising:
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a semiconductor substrate; a device region formed in the semiconductor substrate; at least one conducting pad disposed over a surface of the semiconductor substrate; a protection substrate disposed over the surface of the semiconductor substrate; a spacer layer disposed between the surface of the semiconductor substrate and the protection substrate, wherein the protection substrate and the spacer layer surround a cavity over the device region, the spacer layer has an outer side surface away from the cavity, and the outer side surface of the spacer layer is not a cutting surface; a dielectric layer disposed between the surface of the semiconductor substrate and the spacer layer, wherein the dielectric layer covers the device region and the space layer is disposed over the dielectric layer; and a portion of a sacrificial support layer disposed on the dielectric layer, wherein the portion of the sacrificial support layer is located between the spacer layer and a conducting pad of the at least one conducting pad closest to the spacer layer, and a gap is between the portion of the sacrificial support layer and the spacer layer.
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Specification