Method of forming an inductor with magnetic material

• US 9,449,917 B2
• Filed: 05/24/2015
• Issued: 09/20/2016
• Est. Priority Date: 03/14/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Luo, Cheng-Wei, Yen, Hsiao-Tsung, Kuo, Chin-Wei, Jeng, Min-Chie
• Primary Examiner(s): DANG, PHUC T
• Application Number:
  US14/720,805
• Publication Number:
  US 20150255391A1
• Time in Patent Office: 485 Days
• Field of Search: 257/531
• US Class Current: 1/1
• CPC Class Codes: H01F 17/0033 with the coil helically wound around a magnetic core
• CPC Class Codes: H01F 2017/0066 with a magnetic layer
• CPC Class Codes: H01F 2017/0086 on semiconductor substrate
• CPC Class Codes: H01F 2027/2809 on stacked layers
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. A magnetic layer is positioned within the coil. In another embodiment, a coil is formed on a single substrate, wherein a magnetic layer is positioned within the coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture.

Claims

1. A method for forming a semiconductor device, the method comprising:

receiving a device comprising a first substrate and a first dielectric layer over the first substrate, the first dielectric layer having a first conductive pattern;

receiving an interposer comprising a second substrate and a second dielectric layer over the second substrate, the second dielectric layer having a second conductive pattern;

forming a first magnetic layer on at least one of the interposer and the device;

forming a second magnetic layer on at least one of the interposer and the device, the second magnetic layer being a different layer than the first magnetic layer; and

bonding the device to the interposer using conductive bumps, wherein at least one of the conductive bumps electrically couples the first conductive pattern to the second conductive pattern to form a coil, and wherein the first magnetic layer and the second magnetic layer are interposed between the first conductive pattern and the second conductive pattern after the bonding.

2. The method of claim 1, further comprising forming a through substrate via (TSV) extending through the second substrate, the TSV being electrically coupled to the second conductive pattern.

3. The method of claim 1, wherein the first conductive pattern comprises at least two trace links extending in a first direction, and the second conductive pattern comprises at least two trace links extending in a second direction different from the first direction.

4. The method of claim 1, wherein the first conductive pattern and the second conductive pattern each comprises a ring-shape.

5. The method of claim 1, wherein the first magnetic layer is in contact with one of the first conductive pattern and the second conductive pattern.

6. The method of claim 1, wherein the first magnetic layer is formed on one or more sides of a conductor of the coil.

7. The method of claim 1, wherein the first magnetic layer is in contact with the first conductive pattern and the second magnetic layer is in contact with the second conductive pattern.

8. The method of claim 7, further comprising a third magnetic layer interposed between the first magnetic layer and the second magnetic layer.

9. A method for forming a semiconductor device, the method comprising:

forming a first layer on a first substrate, the first layer comprising a first conductive pattern, the first conductive pattern forming a first portion of a coil;

forming a first patterned magnetic layer on the first conductive pattern, the first patterned magnetic layer having a pattern of the first conductive pattern;

forming a second layer on a second substrate, the second layer comprising a second conductive pattern, the second conductive pattern forming a second portion of the coil; and

electrically coupling the first conductive pattern to the second conductive pattern such that the first patterned magnetic layer is interposed between the first conductive pattern and the second conductive pattern, the electrically coupling forming the coil from the first portion and the second portion.

10. The method of claim 9, wherein the coil spirals around the first patterned magnetic layer.

11. The method of claim 10, further comprising forming a second patterned magnetic layer on the second conductive pattern, the second patterned magnetic layer having a pattern of the second conductive pattern.

12. The method of claim 11, wherein the second patterned magnetic layer extends along sidewalls of the second conductive pattern.

13. The method of claim 9, wherein the first patterned magnetic layer extends along sidewalls of the first conductive pattern.

14. The method of claim 9, wherein the first patterned magnetic layer directly contacts the first conductive pattern.

15. The method of claim 9, wherein the electrically coupling comprises forming solder bumps to electrically couple the first conductive pattern to the second conductive pattern.

16. The method of claim 9, wherein the first patterned magnetic layer physically contacts the first conductive pattern.

17. The method of claim 9, wherein the first patterned magnetic layer is interposed between adjacent traces of the first conductive pattern.

18. A method for forming a semiconductor device, the method comprising:

forming a first conductive pattern on a first substrate;

forming a magnetic layer on the first conductive pattern;

forming a second conductive pattern on a second substrate; and

electrically coupling the first conductive pattern to the second conductive pattern, the first conductive pattern and the second conductive pattern forming a coil, wherein the magnetic layer is in direct physical contact with one of the first conductive pattern and the second conductive pattern.

19. The method of claim 18, wherein the magnetic layer is formed on one or more sides of a first conductive pattern.

20. The method of claim 18, wherein the first conductive pattern has a ring shape in a plan view.