Integrated passive devices

• US 9,449,925 B2
• Filed: 03/01/2013
• Issued: 09/20/2016
• Est. Priority Date: 10/29/2005
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Inventors: Lin, Yaojian, Cao, Haijing, Zhang, Qing, Chen, Kang, Fang, Jianmin
• Primary Examiner(s): Hu, Shouxiang
• Application Number:
  US13/782,939
• Publication Number:
  US 20130175668A1
• Time in Patent Office: 1,299 Days
• Field of Search: 257/E27.111, 257/531, 257/528, 257/532, 257/700, 257/777, 257/737, 257/784, 257/277, 257/359, 257/778, 257/783
• US Class Current: 1/1
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 28/00 Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A semiconductor device has integrated passive circuit elements. A first substrate is formed on a backside of the semiconductor device. The passive circuit element is formed over the insulating layer. The passive circuit element can be an inductor, capacitor, or resistor. A passivation layer is formed over the passive circuit element. A carrier is attached to the passivation layer. The first substrate is removed. A non-silicon substrate is formed over the insulating layer on the backside of the semiconductor device. The non-silicon substrate is made with glass, molding compound, epoxy, polymer, or polymer composite. An adhesive layer is formed between the non-silicon substrate and insulating layer. A via is formed between the insulating layer and first passivation layer. The carrier is removed. An under bump metallization is formed over the passivation layer in electrical contact with the passive circuit element. A solder bump is formed on the under bump metallization.

Claims

1. An intermediate structure for a semiconductor device, comprising:

a first substrate;

a first insulating layer formed over the substrate including a first trench;

an integrated passive device disposed over the first insulating layer;

a second insulating layer disposed over the integrated passive device and first substrate including a second trench aligned with the first trench;

a conductive layer formed over the second insulating layer;

a third insulating layer formed over the second insulating layer and conductive layer;

an insulating material disposed continuously in the first trench and the second trench with the first trench and second trench being devoid of conductive material;

a second substrate disposed over the third insulating layer; and

a non-conductive adhesive layer disposed between the third insulating layer and the second substrate.

2. The intermediate structure for the semiconductor device of claim 1, wherein the first substrate includes silicon material.

3. The intermediate structure for the semiconductor device of claim 1, wherein the first substrate includes non-silicon material.

4. The intermediate structure for the semiconductor device of claim 1, wherein the first substrate is made with a material selected from the group consisting of glass, molding compound, epoxy, polymer, and polymer composite.

5. The intermediate structure for the semiconductor device of claim 1, wherein a portion of the conductive layer is wound to exhibit an inductive property.

6. The intermediate structure for the semiconductor device of claim 1, wherein the integrated passive device includes a capacitor or resistor.

7. An intermediate structure for a semiconductor device, comprising:

a first substrate;

an integrated passive device disposed over the first substrate;

a first insulating layer disposed over the integrated passive device and first substrate, the first insulating layer including a first trench;

a second insulating layer disposed between the first insulating layer and first substrate, the second insulating layer including a second trench aligned with the first trench, the first trench and second trench being devoid of conductive material;

an interconnect structure formed over the first insulating layer;

an adhesive layer including resin deposited over the interconnect structure; and

a second substrate disposed over the adhesive layer.

8. The intermediate structure for the semiconductor device of claim 7, wherein the first substrate includes silicon material.

9. The intermediate structure for the semiconductor device of claim 7, wherein the first substrate includes non-silicon material.

10. The intermediate structure for the semiconductor device of claim 7, wherein the first substrate is made with a material selected from the group consisting of glass, molding compound, epoxy, polymer, and polymer composite.

11. The intermediate structure for the semiconductor device of claim 7, wherein the interconnect structure includes:

a conductive layer formed over the first insulating layer; and

a second insulating layer formed over the first insulating layer and conductive layer.

12. The intermediate structure for the semiconductor device of claim 11, wherein a portion of the conductive layer is wound to exhibit an inductive property.

13. The intermediate structure for the semiconductor device of claim 7, further including:

a via formed in the first insulating layer; and

an insulating material disposed in the via.

14. An intermediate structure for a semiconductor device, comprising:

a non-silicon substrate including a material;

a first insulating layer formed over the non-silicon substrate including a trench in the first insulating layer, the trench filled entirely with a material same as the material of the non-silicon substrate;

an integrated passive device disposed over the first insulating layer;

a second insulating layer disposed over the integrated passive device and non-silicon substrate;

a conductive layer formed over the second insulating layer;

a third insulating layer formed over the first insulating layer and conductive layer; and

an adhesive layer completely covering a surface of the third insulating layer.

15. The intermediate structure for the semiconductor device of claim 14, wherein the material of the non-silicon substrate is selected from the group consisting of glass, molding compound, epoxy, polymer, and polymer composite.

16. The intermediate structure for the semiconductor device of claim 14, wherein the material of the non-silicon substrate includes a resistivity of approximately 1000 ohm-cm.

17. The intermediate structure for the semiconductor device of claim 14, wherein a portion of the conductive layer is wound to exhibit an inductive property.

18. The intermediate structure for the semiconductor device of claim 14, wherein the integrated passive device includes a capacitor or resistor.