Gate structure with hard mask structure formed thereon and method for forming the same

• US 9,449,963 B2
• Filed: 07/03/2014
• Issued: 09/20/2016
• Est. Priority Date: 07/03/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Huang-Kui
• Primary Examiner(s): Armand, Marc
• Assistant Examiner(s): JEFFERSON, QUOVAUNDA
• Application Number:
  US14/323,507
• Publication Number:
  US 20160005731A1
• Time in Patent Office: 810 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS

Abstract

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a first capacitor structure. The first capacitor structure includes a fin structure formed over a substrate and a first gate structure formed over the substrate. In addition, a first portion of the first gate structure overlaps with a portion of the fin structure. The first capacitor structure further includes a first hard mask structure formed over the first portion of the first gate structure and a first conductive structure formed on the first hard mask structure over the first portion of the first gate structure. The first capacitor structure further includes a first contact formed on a second portion of the first gate structure. In addition, the first contact is in direct contact with the second portion of the first gate structure.

Claims

1. A semiconductor structure, comprising:

a first capacitor structure, the first capacitor structure comprising;

a fin structure formed over a substrate;

a first gate structure formed over the substrate, wherein a first portion of the first gate structure overlaps with a portion of the fin structure;

a first hard mask structure formed over the first portion of the first gate structure;

a first conductive structure formed on the first hard mask structure over the first portion of the first gate structure, wherein the first hard mask structure is vertically sandwiched between the first conductive structure and the first gate structure; and

a first contact formed on a second portion of the first gate structure, wherein the first contact is in direct contact with the second portion of the first gate structure.

2. The semiconductor structure as claimed in claim 1, wherein the first portion of the first gate structure is positioned between source and drain regions of the fin structure.

3. The semiconductor structure as claimed in claim 1, wherein the first conductive structure has a first conductive structure width and the first contact has a first contact width, and a ratio of the first conductive structure width to the first contact width is in a range from about 1:

1 to about 1;

3.

4. The semiconductor structure as claimed in claim 1, further comprising:

a transistor structure, the transistor structure comprising;

a second gate structure formed over the substrate, wherein a first portion of the second gate structure overlaps with a portion of the fin structure;

a second hard mask structure formed over the first portion of the second gate structure;

a second contact formed on source and drain regions of the fin structure adjacent to the second gate structure,

wherein the first hard mask structure has a first thickness, and the second hard mask structure has a second thickness substantially equal to the first thickness.

5. The semiconductor structure as claimed in claim 4, wherein the first conductive structure is configured to measure the second thickness of the second hard mask structure through measuring the capacitance-equivalent thickness of the first capacitor.

6. The semiconductor structure as claimed in claim 1, further comprising:

a second capacitor structure, the second capacitor structure comprising;

a third gate structure formed on the substrate, wherein a first portion of the third gate structure overlaps with a portion of the fin structure;

a third hard mask structure formed over the first portion of the third gate structure;

a third conductive structure formed on the third hard mask structure over the first portion of the first gate structure; and

a third contact formed on a second portion of the third gate structure, wherein the third contact is in direct contact with the second portion of the third gate structure.

7. The semiconductor structure as claimed in claim 6, wherein the first conductive structure has a first extending portion extending from the first hard mask structure, and the third conductive structure has a third extending portion extending from the third hard mask structure.

8. The semiconductor structure as claimed in claim 7, wherein the first conductive structure has a first conductive structure width, and the third conductive structure has a third conductive structure width substantially equal to the first conductive structure width.

9. The semiconductor structure as claimed in claim 7, wherein the first extending portion extends from a side of the first hard mask structure away from the third hard mask structure, and the third extending portion extends from a side of the third hard mask structure away from the first hard mask structure.

10. A semiconductor structure, comprising:

a first capacitor structure, the first capacitor structure comprising;

a first gate structure formed over a substrate;

a first hard mask structure formed over a first portion of the first gate structure;

a first conductive structure formed on the first hard mask structure over the first portion of the first gate structure, wherein the first hard mask structure is vertically sandwiched between the first conductive structure and the first gate structure; and

a first contact formed on a second portion of the first gate structure, wherein the first contact is in direct contact with the second portion of the first gate structure; and

a transistor structure, the transistor structure comprising;

a second gate structure formed over the substrate;

a second hard mask structure formed over a first portion of the second gate structure;

a second contact formed on source and drain regions in the substrate adjacent to the second gate structure,

wherein the first hard mask structure has a first thickness, and the second hard mask structure has a second thickness substantially equal to the first thickness.

11. The semiconductor structure as claimed in claim 10, wherein the transistor structure is a fin field effect transistor (finFET) structure comprising a fin structure, and the first portion of the first gate structure overlaps with a portion of the fin structure.

12. The semiconductor structure as claimed in claim 10, wherein the first conductive structure has a first conductive structure width and the first contact has a first contact width, and a ratio of the first conductive structure width to the first contact width is in a range from about 1:

1 to about 1;

3.

13. The semiconductor structure as claimed in claim 10, further comprising:

a second capacitor structure, the second capacitor structure comprising;

a third gate structure formed over the substrate;

a third hard mask structure formed over a first portion of the third gate structure;

a third conductive structure formed on the third hard mask structure over the first portion of the first gate structure; and

a third contact formed on a second portion of the third gate structure, wherein the third contact is in direct contact with the second portion of the third gate structure.

14. The semiconductor structure as claimed in claim 13, wherein the first conductive structure has a first extending portion extending from the first hard mask structure, and the third conductive structure has a third extending portion extending from the third hard mask structure.

15. A method for forming a semiconductor structure, comprising:

forming a first gate structure and a second gate structure over a substrate;

forming first source and drain regions and second source and drain regions in the substrate respectively adjacent to the first gate structure and the second gate structure;

forming a first hard mask structure on the first gate structure and a second hard mask structure on the second gate structure;

forming a first conductive structure on the first hard mask structure and a second contact on the second source and drain regions adjacent to the second gate structure, wherein the first hard mask structure is vertically sandwiched between the first conductive structure and the first gate structure; and

forming a first contact through the first hard mask structure over the first gate structure.

16. The method for forming a semiconductor structure as claimed in claim 15, wherein the first hard mask structure has a first thickness, and the second hard mask structure has a second thickness substantially equal to the first thickness.

17. The method for forming a semiconductor structure as claimed in claim 15, wherein the substrate comprises a fin structure, and a portion of the first gate structure and a portion of the second gate structure are formed over portions of the fin structure.

18. The method for forming a semiconductor structure as claimed in claim 15, wherein the step of forming a first conductive structure on the first hard mask structure and a second contact on the second source and drain regions comprises:

forming a dielectric layer over the first hard mask structure, the second hard mask structure, and the second source and drain regions;

etching the dielectric layer to form a first conductive structure trench over the first hard mask structure and a second contact trench over the second source and drain regions by a first etching process; and

filling the first conductive structure trench and the second contact trench by a first conductive material to form a first conductive structure on the first hard mask structure and the second contact on the second source and drain regions.

19. The method for forming a semiconductor structure as claimed in claim 15, wherein the first conductive structure has a first conductive structure width and the first contact has a first contact width, and a ratio of the first conductive structure width to the first contact width is in a range from about 1:

1 to about 1;

3.

20. The method for forming a semiconductor structure as claimed in claim 15, further comprising:

forming a third gate structure over the substrate;

forming third source and drain regions in the substrate adjacent to the third dummy gate structure;

forming a third hard mask structure on the third gate structure; and

forming a third conductive structure over the third hard mask structure,

wherein the first conductive structure has a first extending portion extending from the first hard mask structure, and the third conductive structure has a third extending portion extending from the third hard mask structure.