Transistor array structure

• US 9,449,967 B1
• Filed: 03/15/2013
• Issued: 09/20/2016
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Roy, Richard S., Leshner, Samuel
• Primary Examiner(s): Nguyen, Tung X
• Assistant Examiner(s): Shah, Neel
• Application Number:
  US13/835,327
• Time in Patent Office: 1,285 Days
• Field of Search: 365/94, 365/104, 365/103, 365/203, 365/156, 365/226, 365/229, 324/762.01, 324/762.09, 324/760.02
• US Class Current: 1/1
• CPC Class Codes: G01R 31/26 Testing of individual semiconductor devices testing or measuring during manufacture or treatment H01L22/00; testing of photovoltaic devices H02S50/10
• CPC Class Codes: G01R 31/2621 for testing field effect transistors, i.e. FET's
• CPC Class Codes: G01R 31/52 Testing for short-circuits, leakage current or ground faults
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate

Abstract

A semiconductor circuit can include a plurality of arrays of transistors having differing characteristics and operating at low voltages and currents. A drain line drive signal may provide a potential to a drain line to which a selected transistor is connected. A row of drain mux circuits can provide reduced leakage current on the drain line drive signal so that more accurate current measurements may be made. A gate line drive signal may provide a potential to a gate line to which the selected transistor is connected. A column of gate line mux circuits can provide a gate line low drive signal to unselected transistors to reduce leakage current in unselected transistors so that more accurate drain current measurements may be made to the selected transistor.

Claims

1. A circuit, comprising:

an array of transistors;

a plurality of drain lines, each drain line coupled to a plurality of the array of transistors in a drain line direction; and

a plurality of drain line multiplexers, each drain line multiplexer having a first drain multiplexer terminal coupled to a drain line drive signal, a second drain multiplexer terminal coupled to a leakage current reduction signal, and a third drain multiplexer terminal coupled to a corresponding one of the plurality of drain lines wherein each one of the plurality of drain line multiplexers includes a first pass gate having a first pass gate controllable impedance path coupled between the first drain multiplexer terminal and the third drain multiplexer terminal and a second pass gate having a second pass gate controllable impedance path coupled between the second drain multiplexer terminal and the third drain multiplexer terminal, and wherein when one of the plurality of drain line multiplexers provides a low impedance path between the first drain multiplexer terminal and the third drain multiplexer terminal, the other of the plurality of drain line multiplexers provides a low impedance path between the second drain multiplexer terminal and the third drain multiplexer terminal.

2. The circuit of claim 1, further including:

a global drain drive signal; and

a third pass gate having a controllable impedance path between the global drain drive signal and the first drain multiplexer terminal.

3. The circuit of claim 1, wherein:

the array of transistors are n-channel insulated gate field effect transistors and the drain line drive signal has about the same potential as the leakage current reduction signal.

4. The circuit of claim 1, wherein:

the array of transistors are p-channel insulated gate field effect transistors and the drain line drive signal has about the same potential as the leakage current reduction signal.

5. The circuit of claim 1, further including:

a plurality of gate lines, each gate line coupled to a plurality of the array of transistors in a gate line direction; and

a plurality of gate line multiplexers, each gate line multiplexer having a first gate multiplexer terminal coupled to a first gate line drive signal, a second gate multiplexer terminal coupled to a second gate line drive signal, and a third gate multiplexer terminal coupled to a corresponding one of the plurality of gate lines wherein when one of the plurality of gate line multiplexers provides a low impedance path between the first gate multiplexer terminal and the third gate multiplexer terminal, the other of the plurality of gate line multiplexers provides a low impedance path between the second gate multiplexer terminal and the third gate multiplexer terminal.

6. The circuit of claim 5, wherein:

each one of the plurality of gate line multiplexers includes

a first pass gate having a first pass gate controllable impedance path coupled between the first gate multiplexer terminal and the third gate multiplexer terminal.

7. The circuit of claim 6, wherein:

each one of the plurality of gate line multiplexers further includes

a second pass gate having a first pass gate controllable impedance path coupled between the second gate multiplexer terminal and the third gate multiplexer terminal.

8. The circuit of claim 5, wherein:

the first gate line drive signal is bound between a first potential and a second potential and the second gate line drive signal has a potential that is outside the bounds of the first gate line drive signal.

9. The circuit of claim 5, wherein:

the plurality of drain line multiplexers receive a first power supply potential and the plurality of gate line multiplexers receive a second power supply potential.

10. The circuit of claim 1, wherein:

the plurality of transistors are insulated gate field effect transistors including a structure having a gate overlying a channel, wherein the channel comprises a substantially undoped channel having a relatively high mobility and a heavily doped screen layer lying a predetermined distance below the transistor gate.

11. The circuit of claim 1, each of the first pass gate and the second pass gate includes a transistor of which structure is different from a structure of a transistor included in the array of transistors.

12. The circuit of claim 1, each of the first pass gate and the second pass gate includes a NMOS transistor and a PMOS transistor, and the array of transistors includes memory transistors.

13. A circuit, comprising:

a first array of transistors;

a first plurality of drain lines, each drain line coupled to a plurality of the first array of transistors in a drain line direction; and

a first plurality of drain line multiplexers, each one of the first plurality of drain line multiplexers having a first drain multiplexer terminal coupled to a drain line drive signal, a second drain multiplexer terminal coupled to a second drain line drive signal, and a third drain multiplexer terminal coupled to a corresponding one of the first plurality of drain lines each one of the first plurality of drain line multiplexers includes a first pass gate having a first pass gate controllable impedance path coupled between the first drain multiplexer terminal and the third drain multiplexer terminal and a second pass gate having a second pass gate controllable impedance path coupled between the second drain multiplexer terminal and the third drain multiplexer terminal, and wherein when one of the first plurality of drain line multiplexers provides a low impedance path between the first drain multiplexer terminal and the third drain multiplexer terminal, the other of the first plurality of first drain line multiplexers provides a low impedance path between the second drain multiplexer terminal and the third drain multiplexer terminal;

a second array of transistors;

a second plurality of drain lines, each drain line coupled to a plurality of the second array of transistors in a drain line direction; and

a second plurality of drain line multiplexers, each one of the second plurality of drain line multiplexers having a first drain multiplexer terminal coupled to the drain line drive signal, a second drain multiplexer terminal coupled to the second drain line drive signal, and a third drain multiplexer terminal coupled to a corresponding one of the second plurality of drain lines wherein when one of the second plurality of drain line multiplexers provides a low impedance path between the first drain multiplexer terminal and the third drain multiplexer terminal, the other of the second plurality of first drain line multiplexers provides a low impedance path between the second drain multiplexer terminal and the third drain multiplexer terminal.

14. The circuit of claim 13, wherein:

the first array of transistors are n-channel insulated gate field effect transistors (IGFETs); and

the second array of transistors are p-channel IGFETs.

15. The circuit of claim 13, wherein:

the first array of transistors include at least two transistors that are different types.

16. The circuit of claim 13, each of the first pass gate and the second pass gate includes a transistor of which structure is different from a structure of a transistor included in the first array of transistors.

17. The circuit of claim 13, each of the first pass gate and the second pass gate includes a NMOS transistor and a PMOS transistor, and the first array of transistors includes memory transistors.