Method for forming lateral super-junction structure

• US 9,450,045 B1
• Filed: 06/23/2015
• Issued: 09/20/2016
• Est. Priority Date: 06/23/2015
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bobde, Madhur, Guan, Lingpeng, Padmanabhan, Karthik, Yilmaz, Hamza
• Primary Examiner(s): Menz, Laura
• Application Number:
  US14/747,961
• Time in Patent Office: 455 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0882 Disposition
• CPC Class Codes: H01L 29/0886 Shape
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7818 the other device being a pn-junction diode

Abstract

A fabrication method to form a lateral superjunction structure in a semiconductor device uses N and P type ion implantations into a base epitaxial layer. In some embodiments, the base epitaxial layer is an intrinsic epitaxial layer or a lightly doped epitaxial layer. The method performs simultaneous N and P type ion implantations into the base epitaxial layer. The epitaxial and implantation processes are repeated successively to form multiple implanted base epitaxial layers on a semiconductor base layer. After the desired number of implanted base epitaxial layers is formed, the semiconductor structure is subjected to annealing to form a lateral superjunction structure including alternate N and P type thin semiconductor regions. In particular, the alternating N and P type thin superjunction layers are formed by the ion implantation process and subsequent annealing. The fabrication method of the present invention ensures good charge control in the lateral superjunction structure.

Claims

1. A method for forming a lateral superjunction structure, comprising:

providing a heavily doped semiconductor substrate of a first conductivity type;

forming a lightly doped semiconductor layer of the first conductivity type on the substrate, the substrate and the lightly doped semiconductor layer forming a semiconductor base layer;

forming a base epitaxial layer on the semiconductor base layer;

performing N-type and P-type implantation into a first region of the base epitaxial layer to introduce both N-type and P-type dopants into the first region of the base epitaxial layer;

repeating the forming a base epitaxial layer and the performing N-type and P-type implantation into the base epitaxial to form a plurality of implanted base epitaxial layers on the semiconductor base layer, the plurality of implanted base epitaxial layers forming a semiconductor structure having a first surface opposite the semiconductor base layer; and

annealing the plurality of implanted base epitaxial layers to activate implanted dopants and to spread out the implanted dopants to form alternating N-type and P-type thin semiconductor regions in the semiconductor structure, wherein the alternating N-type and P-type thin semiconductor regions form the lateral superjunction structure, the alternating N-type and P-type thin semiconductor regions being formed in the first region and being formed parallel to the first surface of the semiconductor structure.

2. The method of claim 1, further comprising:

forming a cap epitaxial layer on the last implanted base epitaxial layer.

3. The method of claim 2, wherein forming a cap epitaxial layer on the last implanted base epitaxial layer comprises:

forming an intrinsic epitaxial layer as the cap epitaxial layer.

4. The method of claim 2, wherein forming a cap epitaxial layer on the last implanted base epitaxial layer comprises:

forming a lightly doped epitaxial layer of N or P type conductivity as the cap epitaxial layer.

5. The method of claim 1, wherein forming a base epitaxial layer on the semiconductor base layer comprises:

forming an intrinsic epitaxial layer as the base epitaxial layer on the semiconductor base layer.

6. The method of claim 1, wherein forming a base epitaxial layer on the semiconductor base layer comprises:

forming a lightly doped epitaxial layer of the N or P type conductivity as the base epitaxial layer on the semiconductor base layer.

7. The method of claim 1, wherein performing N-type and P-type implantation into the first region of the base epitaxial layer comprises:

performing simultaneous N-type and P-type implantation into the first region and the same depth in the base epitaxial layer.

8. The method of claim 1, wherein performing N-type and P-type implantation into the first region of the base epitaxial layer comprises:

performing N-type and P-type implantation into the first region of the base epitaxial layer using an N-type implant dose much greater than a P-type implant dose.

9. The method of claim 8, wherein performing N-type and P-type implantation into the first region of the base epitaxial layer using an N-type implant dose much greater than a P-type implant dose comprises:

performing N-type and P-type implantation into the first region of the base epitaxial layer using an N-type implant dose at least three times greater than the P-type implant dose.

10. The method of claim 1, wherein performing N-type and P-type implantation into the first region of the base epitaxial layer comprises:

performing N-type and P-type implantation using N-type dopants that are much heavier than the P-type dopants.

11. The method of claim 10, wherein performing N-type and P-type implantation using N-type dopants that are much heavier than the P-type dopants comprises:

performing N-type and P-type implantation using arsenic or antimony as N-type dopants and using boron as P-type dopants.

12. The method of claim 1, forming comprising:

forming a P-type buried region and an N-type buried region in the semiconductor base layer; and

forming a P-type buried region and an N-type buried region in one or more base epitaxial layers,

wherein annealing the plurality of implanted base epitaxial layers to activate implanted dopants and to spread out the implanted dopants comprises annealing the plurality of implanted base epitaxial layers to form a P-type vertical doped region from the P-type buried regions and an N-type vertical doped region from the N-type buried regions, the P-type and N-type vertical doped regions being formed perpendicular to the first surface of the semiconductor structure.