Lateral DMOS device with dummy gate

• US 9,450,056 B2
• Filed: 01/17/2012
• Issued: 09/20/2016
• Est. Priority Date: 01/17/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ng, Chun-Wai, Liu, Ruey-Hsin, Cai, Jun, Chou, Hsueh-Liang, Chen, Chi-Chih
• Primary Examiner(s): Gupta, Raj R
• Application Number:
  US13/351,295
• Publication Number:
  US 20130181285A1
• Time in Patent Office: 1,708 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

An LDMOS transistor with a dummy gate comprises an extended drift region formed over a substrate, a drain region formed in the extended drift region, a channel region formed in the extended drift region, a source region formed in the channel region and a dielectric layer formed over the extended drift region. The LDMOS transistor with a dummy gate further comprises an active gate formed over the channel region and a dummy gate formed over the extended drift region. The dummy gate helps to reduce the gate charge of the LDMOS transistor while maintaining the breakdown voltage of the LDMOS transistor.

Claims

1. A semiconductor device comprising:

a substrate of a first conductivity;

a first region of a second conductivity formed over the substrate;

a second region of the second conductivity formed in the first region;

a third region of the first conductivity formed in the first region;

a first dielectric layer with a first thickness formed over the first region, wherein a first side of the first dielectric layer is adjacent to the second region and an edge of the first side of the first dielectric layer is vertically aligned with an edge of the second region;

a second dielectric layer with a second thickness formed with a first side adjacent to a second side of the first dielectric layer, wherein the first thickness is greater than the second thickness, and wherein the first dielectric layer and the second dielectric layer form a step;

a first gate formed over the first dielectric layer, wherein a width of the first dielectric layer is greater than a width of the first gate and the first gate occupies a middle portion of the first dielectric layer, and wherein edge regions of the first dielectric layer are free of the first gate thereon; and

a second gate formed above the second dielectric layer, wherein the second gate is separated from the first gate by a gap and a width of the second dielectric layer is greater than a width of the second gate, and wherein the step is free of a gate material thereon.

2. The semiconductor device of claim 1, wherein the second dielectric layer is formed over the first region and the third region.

3. The semiconductor device of claim 1, wherein the first conductivity is P type and the second conductivity is N type.

4. The semiconductor device of claim 1, further comprising a fourth region of the second conductivity formed above the third region and adjacent to a second side of the second dielectric layer.

5. The semiconductor device of claim 4, further comprising a fifth region of the first conductivity adjacent to the fourth region.

6. The semiconductor device of claim 5, wherein a horizontal distance between the first gate and the second gate is in a range from 0.1 um to 1 um.

7. The semiconductor device of claim 5, further comprising:

a first contact formed over the second region; and

a second contact formed over the third region.

8. The semiconductor device of claim 7, wherein the fifth region is coupled to the fourth region through the second contact.

9. The semiconductor device of claim 1, wherein a thickness of the first gate is substantially equal to a thickness of the second gate.

10. A device comprising:

an extended drift region having a first conductivity type formed over a substrate;

a drain region having the first conductivity type formed in the extended drift region;

a channel region having a second conductivity type formed in the extended drift region;

a source region having the first conductivity type formed in the channel region;

a first dielectric layer formed over the channel region and the extended drift region;

a second dielectric layer formed over the extended drift region, wherein the second dielectric layer is horizontally located between the source region and the drain region and a bottom surface of the second dielectric layer is lower than a top surface of the extended drift region with reference to a top surface of the substrate, wherein a bottom surface of the extended drift region is in direct contact with the top surface of the substrate, and wherein the second dielectric layer is thicker than the first dielectric layer, and wherein the first dielectric layer and the second dielectric layer form a step;

a first gate formed on the first dielectric layer, wherein edge regions on a top surface of the first dielectric layer and adjacent to the step are free of the first gate thereon; and

a second gate formed on the second dielectric layer, wherein the second gate is separated from the first gate by a gap and edge regions on a top surface of the second dielectric layer and adjacent to the step are free of the second gate thereon, and wherein the step is free of a gate material thereon.

11. The device of claim 10, wherein:

the first conductivity type is an n-type conductivity; and

the second conductivity type is a p-type conductivity.

12. The device of claim 10, wherein:

the first conductivity type is a p-type conductivity; and

the second conductivity type is an n-type conductivity.

13. The device of claim 10, further comprising:

a drain contact formed over the drain region; and

a source contact formed over the source region.

14. The device of claim 13, further comprising:

a body contact region formed in the channel region, wherein the body contact region is coupled to the source region through the source contact.

15. The device of claim 10, wherein a horizontal distance between the first gate and the second gate is in a range from 0.1 um to 1 um.

16. A transistor comprising:

a substrate with a first conductivity type;

an extended drift region over the substrate, wherein the extended drift region has a second conductivity type;

a drain region in the extended drift region, wherein the drain region has the second conductivity type;

a channel region in the extended drift region, wherein the channel region has the first conductivity type;

a source region in the channel region, wherein the source region has the second conductivity type;

a first dielectric layer with a first thickness over the channel region and the extended drift region;

a second dielectric layer with a second thickness on the extended drift region, wherein the second dielectric layer is adjacent to the first dielectric layer and a bottom surface of the second dielectric layer is lower than a top surface of the extended drift region with reference to a top surface of the substrate, wherein a bottom surface of the extended drift region is in direct contact with the top surface of the substrate, and wherein the first dielectric layer and the second dielectric layer form a step;

a first gate on the first dielectric layer, wherein a distance from a first edge of the first gate to a first edge of the first dielectric layer is approximately equal to a distance from a second edge of the first gate to a second edge of the first dielectric layer, and wherein a width of the first dielectric layer is greater than a width of the first gate, and wherein edge regions on a top surface of the first dielectric layer and adjacent to the step are free of the first gate thereon; and

a second gate on the second dielectric layer, edge regions on a top surface of the second dielectric layer and adjacent to the step are free of the second gate thereon, and wherein the step is free of a gate material thereon.

17. The transistor of claim 16, wherein the first thickness of the first dielectric layer is in a range from 100 Å

to 200 Å

.

18. The transistor of claim 16, wherein the second thickness of the second dielectric layer is in a range from 500 Å

to 2000 Å

.

19. The transistor of claim 18, further comprising:

a drain contact on the drain region;

a source contact on the source region; and

a body contact region in the channel region, wherein the body contact region is coupled to the source region through the source contact.

20. The transistor of claim 16, wherein the second gate is electrically connected to a bias voltage equal to a rating voltage of the transistor.