Lateral DMOS device with dummy gate
First Claim
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1. A semiconductor device comprising:
- a substrate of a first conductivity;
a first region of a second conductivity formed over the substrate;
a second region of the second conductivity formed in the first region;
a third region of the first conductivity formed in the first region;
a first dielectric layer with a first thickness formed over the first region, wherein a first side of the first dielectric layer is adjacent to the second region and an edge of the first side of the first dielectric layer is vertically aligned with an edge of the second region;
a second dielectric layer with a second thickness formed with a first side adjacent to a second side of the first dielectric layer, wherein the first thickness is greater than the second thickness, and wherein the first dielectric layer and the second dielectric layer form a step;
a first gate formed over the first dielectric layer, wherein a width of the first dielectric layer is greater than a width of the first gate and the first gate occupies a middle portion of the first dielectric layer, and wherein edge regions of the first dielectric layer are free of the first gate thereon; and
a second gate formed above the second dielectric layer, wherein the second gate is separated from the first gate by a gap and a width of the second dielectric layer is greater than a width of the second gate, and wherein the step is free of a gate material thereon.
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Abstract
An LDMOS transistor with a dummy gate comprises an extended drift region formed over a substrate, a drain region formed in the extended drift region, a channel region formed in the extended drift region, a source region formed in the channel region and a dielectric layer formed over the extended drift region. The LDMOS transistor with a dummy gate further comprises an active gate formed over the channel region and a dummy gate formed over the extended drift region. The dummy gate helps to reduce the gate charge of the LDMOS transistor while maintaining the breakdown voltage of the LDMOS transistor.
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Citations
20 Claims
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1. A semiconductor device comprising:
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a substrate of a first conductivity; a first region of a second conductivity formed over the substrate; a second region of the second conductivity formed in the first region; a third region of the first conductivity formed in the first region; a first dielectric layer with a first thickness formed over the first region, wherein a first side of the first dielectric layer is adjacent to the second region and an edge of the first side of the first dielectric layer is vertically aligned with an edge of the second region; a second dielectric layer with a second thickness formed with a first side adjacent to a second side of the first dielectric layer, wherein the first thickness is greater than the second thickness, and wherein the first dielectric layer and the second dielectric layer form a step; a first gate formed over the first dielectric layer, wherein a width of the first dielectric layer is greater than a width of the first gate and the first gate occupies a middle portion of the first dielectric layer, and wherein edge regions of the first dielectric layer are free of the first gate thereon; and a second gate formed above the second dielectric layer, wherein the second gate is separated from the first gate by a gap and a width of the second dielectric layer is greater than a width of the second gate, and wherein the step is free of a gate material thereon. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A device comprising:
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an extended drift region having a first conductivity type formed over a substrate; a drain region having the first conductivity type formed in the extended drift region; a channel region having a second conductivity type formed in the extended drift region; a source region having the first conductivity type formed in the channel region; a first dielectric layer formed over the channel region and the extended drift region; a second dielectric layer formed over the extended drift region, wherein the second dielectric layer is horizontally located between the source region and the drain region and a bottom surface of the second dielectric layer is lower than a top surface of the extended drift region with reference to a top surface of the substrate, wherein a bottom surface of the extended drift region is in direct contact with the top surface of the substrate, and wherein the second dielectric layer is thicker than the first dielectric layer, and wherein the first dielectric layer and the second dielectric layer form a step; a first gate formed on the first dielectric layer, wherein edge regions on a top surface of the first dielectric layer and adjacent to the step are free of the first gate thereon; and a second gate formed on the second dielectric layer, wherein the second gate is separated from the first gate by a gap and edge regions on a top surface of the second dielectric layer and adjacent to the step are free of the second gate thereon, and wherein the step is free of a gate material thereon. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A transistor comprising:
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a substrate with a first conductivity type; an extended drift region over the substrate, wherein the extended drift region has a second conductivity type; a drain region in the extended drift region, wherein the drain region has the second conductivity type; a channel region in the extended drift region, wherein the channel region has the first conductivity type; a source region in the channel region, wherein the source region has the second conductivity type; a first dielectric layer with a first thickness over the channel region and the extended drift region; a second dielectric layer with a second thickness on the extended drift region, wherein the second dielectric layer is adjacent to the first dielectric layer and a bottom surface of the second dielectric layer is lower than a top surface of the extended drift region with reference to a top surface of the substrate, wherein a bottom surface of the extended drift region is in direct contact with the top surface of the substrate, and wherein the first dielectric layer and the second dielectric layer form a step; a first gate on the first dielectric layer, wherein a distance from a first edge of the first gate to a first edge of the first dielectric layer is approximately equal to a distance from a second edge of the first gate to a second edge of the first dielectric layer, and wherein a width of the first dielectric layer is greater than a width of the first gate, and wherein edge regions on a top surface of the first dielectric layer and adjacent to the step are free of the first gate thereon; and a second gate on the second dielectric layer, edge regions on a top surface of the second dielectric layer and adjacent to the step are free of the second gate thereon, and wherein the step is free of a gate material thereon. - View Dependent Claims (17, 18, 19, 20)
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Specification