Replacement gate structure for enhancing conductivity
First Claim
1. A method of forming a semiconductor structure comprising:
- forming a planarization dielectric layer over a semiconductor material portion provided on a substrate;
forming a gate cavity within a planarization dielectric layer, said gate cavity straddling said semiconductor material portion;
forming a stack of a gate dielectric layer and a work function material layer in said gate cavity;
patterning said stack of said gate dielectric layer and said work function material layer, wherein portions of a topmost surface of said substrate and sidewalls of said planarization dielectric layer are physically exposed after patterning said stack; and
forming a conductive material portion on a remaining portion of said work function material layer and directly on said physically exposed portions of sidewalls of said planarization dielectric layer and said top surface of said substrate.
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Accused Products
Abstract
After formation of a gate cavity straddling at least one semiconductor material portion, a gate dielectric layer and at least one work function material layer is formed over the gate dielectric layer. The at least one work function material layer and the gate dielectric layer are patterned such that remaining portions of the at least one work function material layer are present only in proximity to the at least one semiconductor material portion. A conductive material having a greater conductivity than the at least one work function material layer is deposited in remaining portions of the gate cavity. The conductive material portion within a replacement gate structure has the full width of the replacement gate structure in regions from which the at least one work function material layer and the gate dielectric layer are removed.
18 Citations
16 Claims
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1. A method of forming a semiconductor structure comprising:
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forming a planarization dielectric layer over a semiconductor material portion provided on a substrate; forming a gate cavity within a planarization dielectric layer, said gate cavity straddling said semiconductor material portion; forming a stack of a gate dielectric layer and a work function material layer in said gate cavity; patterning said stack of said gate dielectric layer and said work function material layer, wherein portions of a topmost surface of said substrate and sidewalls of said planarization dielectric layer are physically exposed after patterning said stack; and forming a conductive material portion on a remaining portion of said work function material layer and directly on said physically exposed portions of sidewalls of said planarization dielectric layer and said top surface of said substrate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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Specification