Semiconductor memory device having an electrically floating body transistor
First Claim
1. An integrated circuit comprising:
- an array of memory cells formed in a semiconductor, the array comprising;
a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each memory cell of the plurality of memory cells comprising;
a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type;
a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type, wherein the floating body region is bounded on a first side by a first insulating region having a first thickness and on a second side by a second insulating region having a second thickness, wherein the second thickness is greater than the first thickness; and
a gate region above the floating body region and the second insulating region and is insulated from the floating body region by an insulating layer; and
control circuitry configured to provide electrical signals to said buried region.
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Accused Products
Abstract
An IC may include an array of memory cells formed in a semiconductor, including memory cells arranged in rows and columns, each memory cell may include a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type, wherein the floating body region is bounded on a first side by a first insulating region having a first thickness and on a second side by a second insulating region having a second thickness, and a gate region above the floating body region and the second insulating region and is insulated from the floating body region by an insulating layer; and control circuitry configured to provide electrical signals to said buried region.
142 Citations
20 Claims
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1. An integrated circuit comprising:
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an array of memory cells formed in a semiconductor, the array comprising; a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each memory cell of the plurality of memory cells comprising; a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type, wherein the floating body region is bounded on a first side by a first insulating region having a first thickness and on a second side by a second insulating region having a second thickness, wherein the second thickness is greater than the first thickness; and a gate region above the floating body region and the second insulating region and is insulated from the floating body region by an insulating layer; and control circuitry configured to provide electrical signals to said buried region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An integrated circuit comprising:
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an array of memory cells formed in a semiconductor, the array comprising; a plurality of semiconductor memory cells arranged in a matrix of rows and a plurality of columns, wherein the rows of memory cells define a first direction and the columns of memory cells define a second direction, and each semiconductor memory cell of the plurality of semiconductor memory cells comprising; a bipolar device having a floating base region, a first region, a second region, and a gate region wherein; a state of said semiconductor memory cell is stored in said floating base region, said floating base region having a surface, said first region is located at the surface of said floating base region, said second region is located below said floating base region, said second region is commonly connected to at least two of said semiconductor memory cells in said matrix, and said gate region overlays two of said semiconductor memory cells along the column direction, and control circuitry configured to provide electrical signals to said second region. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification