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Semiconductor memory device having an electrically floating body transistor

  • US 9,450,090 B2
  • Filed: 11/02/2015
  • Issued: 09/20/2016
  • Est. Priority Date: 10/04/2010
  • Status: Active Grant
First Claim
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1. An integrated circuit comprising:

  • an array of memory cells formed in a semiconductor, the array comprising;

    a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each memory cell of the plurality of memory cells comprising;

    a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type;

    a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type, wherein the floating body region is bounded on a first side by a first insulating region having a first thickness and on a second side by a second insulating region having a second thickness, wherein the second thickness is greater than the first thickness; and

    a gate region above the floating body region and the second insulating region and is insulated from the floating body region by an insulating layer; and

    control circuitry configured to provide electrical signals to said buried region.

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