Stress in trigate devices using complimentary gate fill materials

• US 9,450,092 B2
• Filed: 11/11/2015
• Issued: 09/20/2016
• Est. Priority Date: 06/23/2008
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Rakshit, Titash, Giles, Martin, Pillarisetty, Ravi, Kavalieros, Jack T.
• Primary Examiner(s): Karimy, Timor
• Application Number:
  US14/938,812
• Publication Number:
  US 20160064562A1
• Time in Patent Office: 314 Days
• Field of Search: 257/368, 257/351, 257/E21.616
• US Class Current: 1/1
• CPC Class Codes: H01L 21/8234 MIS technology , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/7845 the means being a conductive material, e.g. silicided S/D or Gate
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate transistor, thereby increasing the carrier mobility and operating frequency. Embodiments also contemplate method for use of the improved tri-gate device.

Claims

1. A semiconductor device, comprising:

a first channel comprising an N-type material and a first current flow direction along a first major axis of the first channel;

a second channel comprising a P-type material and a second current flow direction along a second major axis of the second channel;

a gate electrode structure disposed on the first and second channels, the gate electrode structure comprising a first metal disposed over the first channel that exerts a tensile stress upon the first channel such that charge carrier mobility in the first channel is improved in the first current flow direction, and the gate electrode structure comprising a second metal disposed over the second channel that exerts a compressive stress upon the second channel such that charge carrier mobility in the second channel is improved in the second current flow direction, wherein the first metal is different than the second metal; and

an isolation structure between the first channel and the second channel, wherein the first metal and the second metal are laterally in contact with one another above the isolation structure.

2. The semiconductor device of claim 1, wherein the first metal has a thickness of 10-100 nm.

3. The semiconductor device of claim 1, wherein the second metal has a thickness of 10-100 nm.

4. The semiconductor device of claim 1, wherein the tensile stress exerted upon the first channel is substantially unequal to the compressive stress exerted upon the second channel.

5. The semiconductor device of claim 1, wherein the first metal comprises copper.

6. The semiconductor device of claim 1, wherein the second metal comprises tungsten.

7. The semiconductor device of claim 1, wherein the first metal comprises copper, and the second metal comprises tungsten.

8. The semiconductor device of claim 1, wherein the substrate is a bulk silicon substrate.

9. The semiconductor device of claim 1, wherein the substrate is a silicon on insulator (SOI) substrate.

10. The semiconductor device of claim 1, wherein the first gate is substantially perpendicular to the first major axis.

11. The semiconductor device of claim 1, wherein the second gate is substantially perpendicular to the second major axis.

12. The semiconductor device of claim 1, wherein the first major axis is parallel with the second major axis.

13. A semiconductor device, comprising:

a first channel comprising an N-type semiconductor body and a first current flow direction along a first major axis of the first channel;

a second channel comprising a P-type semiconductor body and a second current flow direction along a second major axis of the second channel;

a gate electrode structure disposed on the first and second channels, the gate electrode structure comprising a first metal disposed over the first channel that exerts a tensile stress upon the first channel such that charge carrier mobility in the first channel is improved in the first current flow direction, and the gate electrode structure comprising a second metal disposed over the second channel that exerts a compressive stress upon the second channel such that charge carrier mobility in the second channel is improved in the second current flow direction, wherein the first metal is different than the second metal; and

an isolation structure between the first channel and the second channel, wherein the first metal and the second metal are laterally in contact with one another above the isolation structure.

14. The semiconductor device of claim 13, wherein the tensile stress exerted upon the first channel is substantially unequal to the compressive stress exerted upon the second channel.

15. The semiconductor device of claim 13, wherein the first metal comprises copper, and the second metal comprises tungsten.

16. The semiconductor device of claim 13, wherein the substrate is a bulk silicon substrate.

17. The semiconductor device of claim 13, wherein the substrate is a silicon on insulator (SOI) substrate.

18. The semiconductor device of claim 13, wherein the first gate is substantially perpendicular to the first major axis.

19. The semiconductor device of claim 13, wherein the second gate is substantially perpendicular to the second major axis.

20. The semiconductor device of claim 13, wherein the first major axis is parallel with the second major axis.