Current digital-to-analog converter reducing flicker noise

• US 9,450,599 B1
• Filed: 03/01/2016
• Issued: 09/20/2016
• Est. Priority Date: 06/24/2015
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kwon, Sun-Woo, Lee, Myung-Jin
• Primary Examiner(s): Nguyen, Linh
• Application Number:
  US15/057,273
• Time in Patent Office: 203 Days
• Field of Search: 341/135, 341/136, 341144-154
• US Class Current: 1/1
• CPC Class Codes: H03M 1/08 of noise H03M1/0617 takes precedence
• CPC Class Codes: H03M 1/66 Digital/analogue converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H03M 1/747 with equal currents which are switched by unary decoded digital signals

Abstract

A current DAC circuit includes a reference current source, a current mirror, a decoder, and one or more current DAC units. The reference current source provides a reference current to a first node. The current mirror includes first and second PMOS transistors configured to provide a copy current generated by copying the reference current to a second node and coupled, at respective drains, to separate nodes. The current mirror may reduce noise of the first and second PMOS transistors through swapping the separate nodes to which the respective drains of the first and second PMOS transistors are connected periodically according to first and second clock signals. The decoder generates one or more enable signals based on a data input signal. One or more current DAC units generate separate positive currents and negative currents based on the copy current and separate enable signals of the one or more enable signals, respectively.

Claims

1. A current digital-to-analog converter (DAC) circuit, comprising:

a reference current source providing a reference current to a first node;

a current mirror including first and second PMOS transistors, the first and second PMOS transistors being configured to provide a copy current generated based on copying the reference current to a second node, the first and second PMOS transistors being coupled, at respective drains, to separate nodes of the first and second nodes, the current mirror being configured to periodically swap the separate nodes to which the respective drains of the first and second PMOS transistors are connected according to first and second clock signals;

a decoder configured to generate at least one enable signal based on a data input signal; and

at least one current DAC unit, each current DAC unit being configured to generate a separate positive current and a separate negative current based on the copy current and a separate enable signal of the at least one enable signal.

2. The current DAC circuit of claim 1, wherein the noise of the first and second PMOS transistors includes flicker noise.

3. The current DAC circuit of claim 1, wherein an activated duration of the first clock signal and an activated duration of the second clock signal are mutually exclusive.

4. The current DAC circuit of claim 1, wherein the current mirror is configured to periodically swap the separate nodes to which the respective drains of the first and second PMOS transistors are connected according to a period of the first and second clock signals.

5. The current DAC circuit of claim 1, wherein

the current mirror further includes a first switch, a second switch, a third switch, and a fourth switch,

the current mirror is configured to connect a gate of the first PMOS transistor to the first node and connect a drain of the first PMOS transistor a first internal node, when a source of the first PMOS transistor receives a supply voltage;

the current mirror is configured to connect a gate of the second PMOS transistor to the first node and connect a drain of the second PMOS transistor to a second internal node, when a source of the second PMOS transistor receives the supply voltage;

a first terminal of the first switch is connected to the first internal node, a second terminal of the first switch is connected to the first node, and the first switch is configured to be selectively closed according to the first clock signal;

a first terminal of the second switch is connected to the second internal node, a second terminal of the second switch is connected to the second node, and the second switch is configured to be selectively closed according to the first clock signal;

a first terminal of the third switch is connected to the second internal node, a second terminal of the third switch is connected to the first node, and the third switch is configured to be selectively closed according to the second clock signal; and

a first terminal of the fourth switch is connected to the first internal node, a second terminal of the fourth switch is connected to the second node, and the fourth switch is configured to be selectively closed according to the second clock signal.

6. The current DAC circuit of claim 5, wherein

the current mirror is configured to connect the drain of the first PMOS transistor to the first node and connect the drain of the second PMOS transistor to the second node when the first clock signal is activated;

and

the current mirror is configured to connect the drain of the first PMOS transistor to the second node and connect the drain of the second PMOS transistor to the first node when the second clock signal is activated.

7. The current DAC circuit of claim 1, wherein

each current DAC unit of the at least one current DAC unit includes a reference NMOS transistor, a driving NMOS transistor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and a sixth switch;

a first terminal of the first switch is connected to the second node, a second terminal of the first switch is connected to a first internal node, and the first switch is configured to be selectively closed according to a third clock signal;

a first terminal of the second switch is connected to a second internal node, a second terminal of the second switch is connected to a third internal node, and the second switch is configured to be selectively closed according to the third clock signal;

a first terminal of the third switch is connected to the second internal node, a second terminal of the third switch is connected to the first internal node, and the third switch is configured to be selectively closed according to a fourth clock signal;

a first terminal of the fourth switch is connected to the second node, a second terminal of the fourth switch is connected to the third internal node, and the fourth switch is configured to be selectively closed according to the fourth clock signal;

a first terminal of the fifth switch is connected to the second internal node, a second terminal of the fifth switch is configured to output a separate negative current of the at least one negative current based on the fifth switch being closed, and the fifth switch is configured to be selectively closed according to an inversion signal of a separate enable signal of the at least one enable signal;

a first terminal of the sixth switch is connected to the second internal node, a second terminal of the sixth switch is configured to output a separate positive current of the at least one positive current based on the sixth switch being closed, and the sixth switch is configured to be selectively closed according to the separate enable signal;

a drain of the reference NMOS transistor is connected to the first internal node, a gate of the reference NMOS transistor is connected to the second node, and a source of the reference NMOS transistor is configured to receive a ground voltage; and

a drain of the driving NMOS transistor is connected to the third internal node, a gate of the driving NMOS transistor is connected to the second node, and a source of the driving NMOS transistor is configured to receive the ground voltage.

8. The current DAC circuit of claim 7, wherein an activated duration of the third clock signal and an activated duration of the fourth clock signal are mutually exclusive.

9. The current DAC circuit of claim 7, wherein

each current DAC unit is configured to connect the drain of the reference NMOS transistor to the second node and connect the drain of the driving NMOS transistor to the second internal node when the third clock signal is activated;

and

each current DAC unit is configured to connect the drain of the reference NMOS transistor to the second internal node and connect the drain of the driving NMOS transistor to the second node when the fourth clock signal is activated.

10. The current DAC circuit of claim 1, wherein a quantity of activated signals included in the at least one enable signal is proportional to a magnitude of the data input signal.

11. A current digital-to-analog converter (DAC) circuit comprising:

a decoder configured to generate at least one enable signal based on a data input signal; and

at least one internal circuit configured to generate at least one positive current and at least one negative current based on the at least one enable signal,

wherein each internal circuit of the at least one internal circuit includes,

a reference current source configured to generate a separate reference current;

a current mirror including first and second PMOS transistors, the first and second PMOS transistors being coupled, at respective drains, to separate nodes of a first node and a second node, the current mirror being configured to output a separate copy current generated based on copying the separate reference current, the current mirror being configured to periodically swap the separate nodes to which the respective drains of the first and second PMOS transistors are connected according to first and second clock signals; and

a separate current DAC unit configured to generate a separate positive current of the at least one positive current and a separate negative current of the at least one negative current based on the separate copy current and a separate enable signal of the at least one enable signal.

12. The current DAC circuit of claim 11, wherein the noise of the first and second PMOS transistors includes flicker noise.

13. The current DAC circuit of claim 11, wherein an activated duration of the first clock signal and an activated duration of the second clock signal are mutually exclusive.

14. The current DAC circuit of claim 11, wherein

each separate reference current has a common magnitude;

and

each given copy current has a common magnitude.

15. The current DAC circuit of claim 11, wherein the current mirror is configured to periodically swap the separate nodes to which the respective drains of the first and second PMOS transistors are connected according to a period of the first and second clock signals.

16. An apparatus, comprising:

first and second PMOS transistors, the first and second PMOS transistors being configured to receive a reference current from a first node, the first and second PMOS transistors being configured to provide a copy current to a second node, the copy current being generated based on copying the reference current, the first and second PMOS transistors being connected, at respective drains, to separate nodes of the first and second nodes; and

first and second sets of switches, the first set of switches being configured to selectively connect the first and second PMOS transistors to the first node, the second set of switches being configured to selectively connect the first and second PMOS transistors to the second node, the first and second sets of switches being configured to periodically swap the separate nodes to which the respective drains of the first and second PMOS transistors are connected.

17. The apparatus of claim 16, wherein

the first and second sets of switches are configured to periodically swap the separate nodes to which the respective drains of the first and second PMOS transistors are connected according to first and second clock signals.

18. The apparatus of claim 17, further comprising:

a first internal node and a second internal node, the first and second sets of switches being configured to selectively connect the first and second internal nodes to separate ones of the first and second nodes;

wherein the first PMOS transistor includes a source, a gate, and a drain, and the first PMOS transistor is configured to, when the source of the first PMOS transistor receives a supply voltage,

connect the gate of the first PMOS transistor to the first node, and

connect the drain of the first PMOS transistor to the first internal node; and

wherein the second PMOS transistor includes a source, a gate, and a drain, and the second PMOS transistor is configured to, when the source of the second PMOS transistor receives the supply voltage,

connect the gate of the second PMOS transistor to the first node, and

connect the drain of the second PMOS transistor to the second internal node.

19. The apparatus of claim 17, further comprising:

a first switch, a second switch, a third switch, and a fourth switch, wherein,

the first set of switches includes the first and third switches;

the second set of switches includes the second and fourth switches;

a first terminal of the first switch is connected to the first internal node, a second terminal of the first switch is connected to the first node, and the first switch is configured to be selectively closed according to the first clock signal;

a first terminal of the second switch is connected to the second internal node, a second terminal of the second switch is connected to the second node, and the second switch is configured to be selectively closed according to the first clock signal, and

a first terminal of the third switch is connected to the second internal node, a second terminal of the third switch is connected to the first node, and the third switch is configured to be selectively closed according to the second clock signal; and

a first terminal of the fourth switch is connected to the first internal node, a second terminal of the fourth switch is connected to the second node, and the fourth switch is configured to be selectively closed according to the second clock signal.

20. The apparatus of claim 17, wherein

the first and second clock signals are received during respective, mutually-exclusive first and second time periods.