Current digital-to-analog converter reducing flicker noise
First Claim
1. A current digital-to-analog converter (DAC) circuit, comprising:
- a reference current source providing a reference current to a first node;
a current mirror including first and second PMOS transistors, the first and second PMOS transistors being configured to provide a copy current generated based on copying the reference current to a second node, the first and second PMOS transistors being coupled, at respective drains, to separate nodes of the first and second nodes, the current mirror being configured to periodically swap the separate nodes to which the respective drains of the first and second PMOS transistors are connected according to first and second clock signals;
a decoder configured to generate at least one enable signal based on a data input signal; and
at least one current DAC unit, each current DAC unit being configured to generate a separate positive current and a separate negative current based on the copy current and a separate enable signal of the at least one enable signal.
1 Assignment
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Accused Products
Abstract
A current DAC circuit includes a reference current source, a current mirror, a decoder, and one or more current DAC units. The reference current source provides a reference current to a first node. The current mirror includes first and second PMOS transistors configured to provide a copy current generated by copying the reference current to a second node and coupled, at respective drains, to separate nodes. The current mirror may reduce noise of the first and second PMOS transistors through swapping the separate nodes to which the respective drains of the first and second PMOS transistors are connected periodically according to first and second clock signals. The decoder generates one or more enable signals based on a data input signal. One or more current DAC units generate separate positive currents and negative currents based on the copy current and separate enable signals of the one or more enable signals, respectively.
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Citations
20 Claims
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1. A current digital-to-analog converter (DAC) circuit, comprising:
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a reference current source providing a reference current to a first node; a current mirror including first and second PMOS transistors, the first and second PMOS transistors being configured to provide a copy current generated based on copying the reference current to a second node, the first and second PMOS transistors being coupled, at respective drains, to separate nodes of the first and second nodes, the current mirror being configured to periodically swap the separate nodes to which the respective drains of the first and second PMOS transistors are connected according to first and second clock signals; a decoder configured to generate at least one enable signal based on a data input signal; and at least one current DAC unit, each current DAC unit being configured to generate a separate positive current and a separate negative current based on the copy current and a separate enable signal of the at least one enable signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A current digital-to-analog converter (DAC) circuit comprising:
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a decoder configured to generate at least one enable signal based on a data input signal; and at least one internal circuit configured to generate at least one positive current and at least one negative current based on the at least one enable signal, wherein each internal circuit of the at least one internal circuit includes, a reference current source configured to generate a separate reference current; a current mirror including first and second PMOS transistors, the first and second PMOS transistors being coupled, at respective drains, to separate nodes of a first node and a second node, the current mirror being configured to output a separate copy current generated based on copying the separate reference current, the current mirror being configured to periodically swap the separate nodes to which the respective drains of the first and second PMOS transistors are connected according to first and second clock signals; and a separate current DAC unit configured to generate a separate positive current of the at least one positive current and a separate negative current of the at least one negative current based on the separate copy current and a separate enable signal of the at least one enable signal. - View Dependent Claims (12, 13, 14, 15)
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16. An apparatus, comprising:
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first and second PMOS transistors, the first and second PMOS transistors being configured to receive a reference current from a first node, the first and second PMOS transistors being configured to provide a copy current to a second node, the copy current being generated based on copying the reference current, the first and second PMOS transistors being connected, at respective drains, to separate nodes of the first and second nodes; and first and second sets of switches, the first set of switches being configured to selectively connect the first and second PMOS transistors to the first node, the second set of switches being configured to selectively connect the first and second PMOS transistors to the second node, the first and second sets of switches being configured to periodically swap the separate nodes to which the respective drains of the first and second PMOS transistors are connected. - View Dependent Claims (17, 18, 19, 20)
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Specification