High quality log likelihood ratios determined using two-index look-up table

• US 9,450,610 B1
• Filed: 12/01/2014
• Issued: 09/20/2016
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Ip Gem Group, LLC
• Original Assignee: Microsemi Storage Solutions, Inc (Microchip Technology Incorporated)
• Inventors: Micheloni, Rino, Marelli, Alessia, Norrie, Christopher I. W.
• Primary Examiner(s): Chaudry, M. Mujtaba
• Application Number:
  US14/557,214
• Time in Patent Office: 659 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: H03M 13/1111 Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
• CPC Class Codes: H03M 13/1117 using approximations for check node processing, e.g. an outgoing message is depending on the signs and the minimum over the magnitudes of all incoming messages according to the min-sum rule
• CPC Class Codes: H03M 13/1137 Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
• CPC Class Codes: H03M 13/3723 using means or methods for the initialisation of the decoder
• CPC Class Codes: H03M 13/6325 Error control coding in combination with demodulation

Abstract

A nonvolatile memory controller includes memory storage configured to store a two-index look-up table that includes a Log-Likelihood Ratio (LLR), hard-and-soft-decision bits associate with the LLR and a neighboring cell read pattern associated with the LLR. Read circuitry is configured to perform a plurality of reads of a cell of a nonvolatile memory storage module at different read voltage levels to generate target cell hard-and-soft-decision bits and configured to read neighboring cells to generate neighboring cell reads. Neighboring cell processing circuitry combines the neighboring cell reads to generate a neighboring cell read pattern. Look-up circuitry accesses the two-index look-up table using the target cell hard-and-soft-decision bits and the neighboring cell read pattern to identify the corresponding LLR for use in Low-Density Parity Check (LDPC) decoding of a codeword stored in the nonvolatile memory storage module.

Claims

1. A method comprising:

storing one or more two-index Log-Likelihood Ratio (LLR) look-up table in a memory controller, the one or more two-index LLR look-up table including a LLR, the hard-and-soft-decision bits associated with the LLR and the neighboring cell read pattern associated with the LLR;

performing a plurality of reads of a target cell of a nonvolatile memory storage module at different read voltage levels to generate a plurality of target cell hard-and-soft-decision bits associated with a bit stored in the target cell, wherein the bit stored in the target cell is part of a codeword stored in the nonvolatile memory storage module;

performing reads of a plurality of neighboring cells to the target cell of the nonvolatile memory storage module to generate a plurality of neighboring cell reads, each of the neighboring cells in the plurality of neighboring cells adjoining the target cell;

combining the results of the neighboring cell reads to generate a neighboring cell read pattern that corresponds to the pattern of the neighboring cell reads; and

accessing the one or more two-index LLR look-up table using the plurality of target cell hard-and-soft-decision bits and the generated neighboring cell read pattern to identify the corresponding LLR; and

sending the identified LLR to a Low-Density Party Check (LDPC) decoder for decoding of the codeword stored in the nonvolatile memory storage module.

2. The method of claim 1, wherein each of the reads of neighboring cells is representative of a logical “

1”

or a logical “

0” and

combining the results of the neighboring cell reads to generate a neighboring cell read pattern further comprises, concatenating the neighboring cell reads representative of a logical “

1”

or representative of a logical “

0”

to generate the neighboring cell read pattern.

3. The method of claim 1, wherein performing a plurality of reads of a target cell of a nonvolatile memory storage module at different read voltage levels to generate a plurality of target cell hard-and-soft-decision bits further comprises generating an index that identifies the threshold voltage region corresponding to the threshold voltage of the bit stored in the target cell.

4. The method of claim 1, wherein the performing a plurality of reads of a target cell of a nonvolatile memory storage module further comprises:

performing a plurality of reads of a target cell of a nonvolatile memory storage module to generate a plurality of reads associated with a bit stored in the target cell;

analyzing the results from the plurality of reads of the target cell to identify a threshold voltage region corresponding to the threshold voltage of the bit stored in the target cell; and

generating the plurality of target cell hard-and-soft-decision bits corresponding to the identified threshold voltage region.

5. The method of claim 1, wherein performing a plurality of reads of a target cell of a nonvolatile memory storage module comprises performing a first read of the target cell at a hard-decision reference voltage level and performing a plurality of additional reads of the target cell at soft-decision reference voltage levels proximate the hard-decision reference voltage level, the memory controller operable for analyzing the plurality of reads to generate the plurality of target cell hard-and-soft-decision bits associated with a bit stored in the cell.

6. The method of claim 1 further comprising:

performing a first read of the target cell of a nonvolatile memory storage module cell at a hard-decision reference voltage and performing a plurality of additional reads of the target cell at soft-decision reference voltages following the first read of the target cell; and

wherein the one or more two-index LLR look-up table comprises a first two-index LLR look-up table corresponding to a first state of the target cell and a second two-index LLR look-up table corresponding to a second state of the target cell, the accessing the one or more two-index LLR look-up table further comprising indexing the first two-index LLR look-up table when the first read of the target cell indicates that the target cell has the first state and indexing the second two-index LLR look-up table when the first read of the target cell indicates that the cell has the second state.

7. The method of claim 1, wherein performing reads of a plurality of neighboring cells further comprises performing a read of all cells adjoining the target cell, the method further comprising:

reading test memory cells of one or more test nonvolatile memory device to identify a LLR corresponding to each possible pattern of reads of a test memory cell and neighboring memory cells, the test memory cell read at the plurality of different voltage levels; and

storing each identified LLR value, the target cell hard-and-soft-decision bits associated with the identified LLR and the neighboring cell read pattern associated with the identified LLR in the one or more two-index LLR look-up table.

8. The method of claim 1, further comprising concatenating the results of the neighboring cell reads and the target cell hard-and-soft-decision bits and wherein the accessing the one or more two-index LLR look-up table further comprises accessing the one or more two-index LLR look-up table using the combined plurality of target cell hard-and-soft-decision bits corresponding to the identified threshold voltage region and the generated neighboring cell read pattern to identify the corresponding LLR for use in LDPC decoding of a codeword stored in the nonvolatile memory storage module.

9. The method of claim 1, further comprising a neighboring cell look-up table that includes the neighboring cell read patterns, hard-decision bits, and corresponding common neighboring cell read pattern indexes to the two-index LLR look-up table, at least some of the common neighboring cell read pattern indexes associated with more than one neighboring cell read pattern, each LLR in the two-index LLR look-up table associated with one of the common neighboring cell read pattern indexes and one set of hard-and-soft-decision bit values.

10. A nonvolatile memory controller comprising:

memory storage configured to store one or more two-index Log-Likelihood Ratio (LLR) look-up table that includes a LLR, hard-and-soft decision bits associated with the LLR and a neighboring cell read pattern associated with the LLR;

read circuitry configured to perform a plurality of reads of a target cell of a nonvolatile memory storage module at different read voltage levels to generate a plurality of target cell hard-and-soft-decision bits associated with a bit stored in the target cell and configured for performing reads of a plurality of neighboring cells to the target cell of the nonvolatile memory storage module to generate a plurality of neighboring cell reads, each of the neighboring cells in the plurality of neighboring cells adjoining the target cell, wherein the bit stored in the target cell is part of a codeword stored in the nonvolatile memory storage module;

neighboring cell processing circuitry configured to combine the results of the neighboring cell reads to generate a neighboring cell read pattern that corresponds to the pattern of the neighboring cell reads; and

look-up circuitry coupled to the neighboring cell circuitry and the read circuitry, the look-up circuitry configured to access the one or more two-index LLR look-up table using the plurality of target cell hard-and-soft-decision bits and the generated neighboring cell read pattern to identify the corresponding LLR for use in LDPC decoding of the codeword stored in the nonvolatile memory storage module.

11. The nonvolatile memory controller of claim 10, wherein the neighboring cell processing circuitry is configured to concatenate values indicating the results from each of the neighboring cell reads to generate the neighboring cell read pattern.

12. The nonvolatile memory controller of claim 11, wherein the look-up circuitry is configured to index the one or more two-index LLR look-up table using the plurality of target cell hard-and-soft-decision bits as a first index and the generated neighboring cell read pattern as a second index, to identify the corresponding LLR for use in LDPC decoding of the codeword stored in the nonvolatile memory storage module.

13. The nonvolatile memory controller of claim 12, wherein each of the reads of neighboring cells is representative of a logical “

1”

or a logical “

0” and

wherein the neighboring cell processing circuitry is further configured to combine the results of the neighboring cell reads by concatenating the neighboring cell reads representative of a logical “

1”

or representative of a logical “

0”

to generate the neighboring cell read pattern.

14. The nonvolatile memory controller of claim 11 wherein the read circuitry is configured to perform a first read of the target cell at a hard-decision reference voltage and perform a plurality of additional reads of the target cell following the first read of the target cell at soft-decision reference voltages;

and

wherein the at least one two-index LLR look-up table comprises a first two-index LLR look-up table corresponding to a first state of the target cell and a second two-index LLR look-up table corresponding to a second state of the target cell, the indexing the one or more two-index LLR look-up table further comprising indexing the first two-index LLR look-up table when the first read of the target cell indicates that the target cell has the first state and indexing the second two-index LLR look-up table when the first read of the target cell indicates that the target cell has the second state.

15. The nonvolatile memory controller of claim 11 wherein the one or more two-index LLR look-up table includes a LLR, the soft reads bits associated with the LLR and the neighboring cell read pattern associated with the LLR for all possible combinations of target cell hard-and-soft-decision bits and neighboring cell read patterns.

16. The nonvolatile memory controller of claim 11 wherein the one or more two-index LLR look-up table further comprises a neighboring cell look-up table that includes the neighboring cell read patterns, hard-decision bits and corresponding common neighboring cell read pattern indexes to the two-index LLR look-up table, at least some of the common neighboring cell read pattern indexes associated with more than one neighboring cell read pattern, each LLR in the two-index LLR look-up table associated with one of the common neighboring cell read pattern indexes and one set of hard-and-soft-decision bit values.

17. The nonvolatile memory controller of claim 16 wherein the cell is a Multi-Level Cell (MLC).

18. A system comprising:

a LDPC (Low-Density Parity Check) encoder configured to generate a codeword;

a nonvolatile memory storage module configured to store the codeword;

memory storage configured to store one or more Log-Likelihood Ratio (LLR) look-up table that includes a LLR, soft reads bits associated with the LLR and a neighboring cell read pattern associated with the LLR;

read circuitry configured to perform a plurality of reads of a target cell of the nonvolatile memory storage module at different read voltage levels to generate a plurality of target cell hard-and-soft-decision bits associated with a bit of the codeword that is stored in the target cell and configured for performing reads of a plurality of neighboring cells to the target cell of the nonvolatile memory storage module to generate a plurality of neighboring cell reads, each of the neighboring cells in the plurality of neighboring cells adjoining the target cell;

neighboring cell processing circuitry configured to combine the results of the neighboring cell reads to generate a neighboring cell read pattern that corresponds to the pattern of the neighboring cell reads;

look-up circuitry coupled to the neighboring cell processing circuitry and the read circuitry, the look-up circuitry configured to access the one or more LLR look-up table using the plurality of target cell hard-and-soft-decision bits and the generated neighboring cell read pattern to identify the corresponding LLR; and

a LDPC decoder coupled to the look-up circuitry, the LDPC decoder configured to use the identified LLR to decode the codeword.

19. The system of claim 18, wherein the read circuitry further comprises read processing circuitry configured to analyze the results from the plurality of reads of the target cell to identify a threshold voltage region corresponding to the threshold voltage of the bit stored in the target cell and configured to generate the plurality of target cell hard-and-soft-decision bits corresponding to the identified threshold voltage region.

20. The system of claim 19, wherein the cell is a Multi-Level Cell (MLC).