High quality log likelihood ratios determined using two-index look-up table
First Claim
1. A method comprising:
- storing one or more two-index Log-Likelihood Ratio (LLR) look-up table in a memory controller, the one or more two-index LLR look-up table including a LLR, the hard-and-soft-decision bits associated with the LLR and the neighboring cell read pattern associated with the LLR;
performing a plurality of reads of a target cell of a nonvolatile memory storage module at different read voltage levels to generate a plurality of target cell hard-and-soft-decision bits associated with a bit stored in the target cell, wherein the bit stored in the target cell is part of a codeword stored in the nonvolatile memory storage module;
performing reads of a plurality of neighboring cells to the target cell of the nonvolatile memory storage module to generate a plurality of neighboring cell reads, each of the neighboring cells in the plurality of neighboring cells adjoining the target cell;
combining the results of the neighboring cell reads to generate a neighboring cell read pattern that corresponds to the pattern of the neighboring cell reads; and
accessing the one or more two-index LLR look-up table using the plurality of target cell hard-and-soft-decision bits and the generated neighboring cell read pattern to identify the corresponding LLR; and
sending the identified LLR to a Low-Density Party Check (LDPC) decoder for decoding of the codeword stored in the nonvolatile memory storage module.
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Abstract
A nonvolatile memory controller includes memory storage configured to store a two-index look-up table that includes a Log-Likelihood Ratio (LLR), hard-and-soft-decision bits associate with the LLR and a neighboring cell read pattern associated with the LLR. Read circuitry is configured to perform a plurality of reads of a cell of a nonvolatile memory storage module at different read voltage levels to generate target cell hard-and-soft-decision bits and configured to read neighboring cells to generate neighboring cell reads. Neighboring cell processing circuitry combines the neighboring cell reads to generate a neighboring cell read pattern. Look-up circuitry accesses the two-index look-up table using the target cell hard-and-soft-decision bits and the neighboring cell read pattern to identify the corresponding LLR for use in Low-Density Parity Check (LDPC) decoding of a codeword stored in the nonvolatile memory storage module.
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Citations
20 Claims
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1. A method comprising:
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storing one or more two-index Log-Likelihood Ratio (LLR) look-up table in a memory controller, the one or more two-index LLR look-up table including a LLR, the hard-and-soft-decision bits associated with the LLR and the neighboring cell read pattern associated with the LLR; performing a plurality of reads of a target cell of a nonvolatile memory storage module at different read voltage levels to generate a plurality of target cell hard-and-soft-decision bits associated with a bit stored in the target cell, wherein the bit stored in the target cell is part of a codeword stored in the nonvolatile memory storage module; performing reads of a plurality of neighboring cells to the target cell of the nonvolatile memory storage module to generate a plurality of neighboring cell reads, each of the neighboring cells in the plurality of neighboring cells adjoining the target cell; combining the results of the neighboring cell reads to generate a neighboring cell read pattern that corresponds to the pattern of the neighboring cell reads; and accessing the one or more two-index LLR look-up table using the plurality of target cell hard-and-soft-decision bits and the generated neighboring cell read pattern to identify the corresponding LLR; and sending the identified LLR to a Low-Density Party Check (LDPC) decoder for decoding of the codeword stored in the nonvolatile memory storage module. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A nonvolatile memory controller comprising:
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memory storage configured to store one or more two-index Log-Likelihood Ratio (LLR) look-up table that includes a LLR, hard-and-soft decision bits associated with the LLR and a neighboring cell read pattern associated with the LLR; read circuitry configured to perform a plurality of reads of a target cell of a nonvolatile memory storage module at different read voltage levels to generate a plurality of target cell hard-and-soft-decision bits associated with a bit stored in the target cell and configured for performing reads of a plurality of neighboring cells to the target cell of the nonvolatile memory storage module to generate a plurality of neighboring cell reads, each of the neighboring cells in the plurality of neighboring cells adjoining the target cell, wherein the bit stored in the target cell is part of a codeword stored in the nonvolatile memory storage module; neighboring cell processing circuitry configured to combine the results of the neighboring cell reads to generate a neighboring cell read pattern that corresponds to the pattern of the neighboring cell reads; and look-up circuitry coupled to the neighboring cell circuitry and the read circuitry, the look-up circuitry configured to access the one or more two-index LLR look-up table using the plurality of target cell hard-and-soft-decision bits and the generated neighboring cell read pattern to identify the corresponding LLR for use in LDPC decoding of the codeword stored in the nonvolatile memory storage module. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. A system comprising:
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a LDPC (Low-Density Parity Check) encoder configured to generate a codeword; a nonvolatile memory storage module configured to store the codeword; memory storage configured to store one or more Log-Likelihood Ratio (LLR) look-up table that includes a LLR, soft reads bits associated with the LLR and a neighboring cell read pattern associated with the LLR; read circuitry configured to perform a plurality of reads of a target cell of the nonvolatile memory storage module at different read voltage levels to generate a plurality of target cell hard-and-soft-decision bits associated with a bit of the codeword that is stored in the target cell and configured for performing reads of a plurality of neighboring cells to the target cell of the nonvolatile memory storage module to generate a plurality of neighboring cell reads, each of the neighboring cells in the plurality of neighboring cells adjoining the target cell; neighboring cell processing circuitry configured to combine the results of the neighboring cell reads to generate a neighboring cell read pattern that corresponds to the pattern of the neighboring cell reads; look-up circuitry coupled to the neighboring cell processing circuitry and the read circuitry, the look-up circuitry configured to access the one or more LLR look-up table using the plurality of target cell hard-and-soft-decision bits and the generated neighboring cell read pattern to identify the corresponding LLR; and a LDPC decoder coupled to the look-up circuitry, the LDPC decoder configured to use the identified LLR to decode the codeword. - View Dependent Claims (19, 20)
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Specification