Memory module with integrated error correction

• US 9,450,614 B2
• Filed: 09/03/2014
• Issued: 09/20/2016
• Est. Priority Date: 09/13/2013
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A., Best, Scott C.
• Primary Examiner(s): Britt, Cynthia
• Assistant Examiner(s): GANDHI, DIPAKKUMAR B
• Application Number:
  US14/475,619
• Publication Number:
  US 20150082119A1
• Time in Patent Office: 748 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: H03M 13/1525 Determination and particular use of error location polynomials
• CPC Class Codes: H03M 13/19 Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
• CPC Class Codes: H03M 13/617 Polynomial operations, e.g. operations related to generator polynomials or parity-check polynomials

Abstract

A memory system includes a memory module that supports error detection and correction (EDC) in a manner that relieves a memory controller or processor of some or all of the computational burden associated with EDC. Individual EDC components perform EDC functions on subsets of the data, and share data between themselves using relatively short, fast interconnections.

Claims

1. A memory module comprising:

memory components to communicate data signals and syndrome signals;

error-detection components each having;

a first interface connected to a respective subset of the memory components to receive a respective subset of the data signals and a respective subset of the syndrome signals;

error-detection logic to detect errors in the respective subset of the data signals using the respective subset of the syndrome signals, the error-detection logic to issue error-detected data signals, the error-detected data signals having a first portion and a second portion; and

a second interface to combine the first portion of the error-detected data signals with the second portion of the error-detected data signals from an adjacent one of the error-detection components; and

a module connector coupled to the second interface of each of the error-detection components to communicate the error-detected data signals from the error-detection components to a controller.

2. The module of claim 1, wherein the error-detection components comprise error-detection logic and error-correction logic, each of the error-detection components to correct the errors in the respective subset of the data signals responsive to the respective subset of the syndrome signals.

3. The module of claim 1, the module connector to receive second data signals and convey subsets of the second data signals to the respective error-detection components, the error-detection components to generate respective second syndrome signals responsive to the subsets of the second data signals.

4. The module of claim 1, further comprising data connections between the adjacent ones of the error-detection components communicate the second portion of the respective subset of the data signals between the adjacent ones of the error-detection components.

5. The module of claim 4, the error-detection components further having serializers to serialize the first portion of the error-detected data signals and the second portion of the error-detected data signals from the adjacent one of the error-detection components.

6. The module of claim 1, each error-detection component further having a repair memory element to substitute for an address location of the memory components.

7. A memory system comprising:

a controller to communicate data of a data width as parallel data bits;

a data bus connected to the controller to convey the data, the data bus including paths to convey the parallel data bits; and

a memory module coupled to the controller via the data bus to store the data, the memory module including;

error-detection components each having;

a controller interface coupled to a respective subset of the paths to receive a respective subset of the data bits, the subset including a first portion of the subset of the data bits and a second portion of the subset of the data bits;

a lateral interface coupled to an adjacent one of the error-detection components to convey the second portion of the subset of the data bits from the adjacent one of the error-detection components;

syndrome logic coupled to the controller interface and the lateral interface to calculate respective syndromes for the first portion of the subset of data bits and the second portion of the subset of data bits from the adjacent one of the error-detection components; and

a memory-component interface to transmit the subsets of the data bits and the syndromes; and

memory components each coupled to the memory-component interface of at least one of the error-detection components, the memory components to store the subsets of the data bits and the syndromes.

8. The memory system of claim 7, the memory-component interface of each of the error-detection components to read the stored subsets of the bits and the syndromes, each of the error-detection components to detect errors in respective stored subsets using respective syndromes.

9. The memory system of claim 8, wherein the error-detection components comprise error-detection logic and error-correction logic, each of the error-detection components to correct the errors in the respective stored subsets, using the respective syndromes, to produce error-corrected data.

10. The memory system of claim 9, each error-detection component further including a serializer to serialize a first portion of the error-corrected data from a first of the error-detection components and a second portion of the error-corrected data from a second of the error-detection components.

11. The memory system of claim 10, wherein the first portion is of a first data width and the second portion is of a second data width different from the first data width.

12. The memory system of claim 11, wherein the ratio of the first and second data widths varies between the error-detection components.

13. The memory system of claim 7, each error-detection component further having a repair memory element to substitute for an address location of the memory components.

14. A method for correcting read errors from memory components, the method comprising:

reading an M-bit sequence of N-bit words from the memory components;

dividing the M-bit sequence of N-bit words into M-bit sequences of P-bit sub-words;

separately deserializing each of the M-bit sequences of P-bit sub-words into a respective data subset and a respective syndrome;

correcting errors in each data subset using the respective syndrome to produce first error-free data subsets;

combining differently sized portions of the first error-free data subsets to produce second error-free data subsets;

serializing the second error-free data subsets; and

combining the serialized second error-free data subsets into an M-bit sequence of R-bit words, wherein R is less than N;

wherein M, P, R, and N are integers;

each of M, P, and R is at least one; and

N is at least two.

15. The method of claim 14, where N is seventy-two and R is sixty-four.

16. The method of claim 15, where M is four or eight.

17. The method of claim 14, where P is eight.

18. The method of claim 14, further comprising conveying the M-bit sequence of R-bit words to a controller component.

19. The method of claim 14, further comprising providing separate components for each of the P-bit subwords.

20. The method of claim 19, wherein each of the components combines two portions of the first error-free data subsets to produce one of the second error-free data subsets.