System and method for capacity planning for systems with multithreaded multicore multiprocessor resources

• US 9,450,806 B2
• Filed: 07/21/2014
• Issued: 09/20/2016
• Est. Priority Date: 08/22/2007
• Status: Expired due to Fees

• Current Assignee: CA, Inc. (d/b/a CA Technologies) (Broadcom, Inc.)
• Original Assignee: CA, Inc. (d/b/a CA Technologies) (Broadcom, Inc.)
• Inventors: Zink, Kenneth C., Neuse, Douglas M., Walton, Christopher B.
• Primary Examiner(s): Do, Thuan
• Application Number:
  US14/336,703
• Publication Number:
  US 20150039753A1
• Time in Patent Office: 792 Days
• Field of Search: 716/101
• US Class Current: 1/1
• CPC Class Codes: G06F 11/3428 Benchmarking
• CPC Class Codes: G06F 11/3442 for planning or managing the needed capacity
• CPC Class Codes: G06F 11/3447 Performance evaluation by modeling
• CPC Class Codes: H04L 41/022 Multivendor or multi-standard integration
• CPC Class Codes: H04L 43/04 Processing captured monitoring data, e.g. for logfile generation
• CPC Class Codes: H04L 67/51 Discovery or management thereof, e.g. service location protocol [SLP] or web services
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method for expressing a hierarchy of scalabilities in complex systems, including a discrete event simulation and an analytic model, for analysis and prediction of the performance of multi-chip, multi-core, multi-threaded computer processors is provided. Further provided is a capacity planning tool for migrating data center systems from a source configuration which may include source systems with multithreaded, multicore, multichip central processing units to a destination configuration which may include destination systems with multithreaded, multicore and multichip central processing units, wherein the destination systems may be different than the source systems. Apparatus and methods are taught for the assembling of and utilization of linear and exponential scalability factors in the capacity planning tool when a plurality of active processor threads populate processors with multiple chips, multiple cores per chip and multiple threads per core.

Claims

1. A method of determining a set of scalability factors for linear and exponential scaling characteristics of an operating system for use in analyzing system performance for a source system configuration and a destination system configuration to determine a system performance level, the method comprising:

receiving a set of CPU performance data;

storing the set of CPU performance data in an internal CPU performance repository;

deriving an analysis of the set of CPU performance data by a set of characteristics of the operating system, a chip architecture set, a number of chips, a number of cores per chip, and a number of supported threads per core;

wherein the analysis is derived using a discrete event simulation or a standard queuing theory analysis;

determining the set of scalability factors based on the analysis;

comparing the system performance level with an expected system criteria;

determining if the system performance level meets the expected system criteria;

adjusting the destination system configuration if the system performance level does not meet the expected system criteria; and

selecting the destination system configuration for implementation when the system performance level meets the expected system criteria.

2. The method of claim 1, further comprising:

comparing the system performance level with an expected system criteria;

determining if the system performance level meets the expected system criteria;

adjusting the destination system configuration if the system performance level does not meet the expected system criteria; and

selecting the destination system configuration for implementation when the system performance level meets the expected system criteria.

3. A capacity planning system to determine a destination system configuration when planning and implementing a system migration from a source system configuration having a first set of servers with a first set of nodes, a first set of disk drives, a first set of memory, and a first set of NICS to a destination system configuration having a second set of servers with a second set of nodes, a second set of disk drives, a second set of memory, and a second set of NICS, wherein the first set of servers includes a first set of processor chips, each processor chip of the first set of processor chips having a first set of microprocessor cores and a first set of processor threads for each microprocessor core of the first set of microprocessor cores capable of executing multiple program tasks, and wherein the second set of servers includes a second set of processor chips, each processor chip of the second set of processor chips having a second set of microprocessor cores and a second set of processor threads for each microprocessor core of the second set of microprocessor cores capable of executing a plurality of program tasks, the capacity planning system comprising:

a set of source parameters describing the first set of servers;

a set of destination parameters describing the second set of servers;

wherein the capacity planning system is programmed to receive a set of CPU performance data from a set of external CPU data repositories, store the CPU performance data in a set of internal repositories, and analyze the set of CPU performance data using a discrete event simulation or a standard queuing theory analysis, to create a scalability fit with a linear component and an exponential component;

wherein the capacity planning system is further programmed to determine the destination system configuration and performance from the scalability fit, the set of source parameters and the set of destination parameters;

wherein the set of CPU performance data includes a tabulated set of records; and

,

wherein each record of the tabulated set of records contains a system description, an operating system type, a processor chip type, a processor clock speed, a number of chips, a number of cores per chip, a number of processor threads per core, a measured single thread performance, and a measured throughput performance rate.