Abstracting a multithreaded processor core to a single threaded processor core

• US 9,454,389 B2
• Filed: 02/25/2015
• Issued: 09/27/2016
• Est. Priority Date: 01/30/2007
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Inventors: Norton, Scott J., Kim, Hyun
• Primary Examiner(s): SWIFT, CHARLES M
• Application Number:
  US14/631,286
• Publication Number:
  US 20150169377A1
• Time in Patent Office: 580 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 2209/5018 Thread allocation
• CPC Class Codes: G06F 2209/5021 Priority
• CPC Class Codes: G06F 9/455 Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
• CPC Class Codes: G06F 9/45504 Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
• CPC Class Codes: G06F 9/45533 Hypervisors; Virtual machine monitors
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects
• CPC Class Codes: G06F 9/48 Program initiating; Program switching, e.g. by interrupt
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system
• CPC Class Codes: G06F 9/485 Task life-cycle, e.g. stopping, restarting, resuming execution G06F9/4881 takes precedence
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: G06F 9/50 Allocation of resources, e.g. of the central processing unit [CPU]
• CPC Class Codes: G06F 9/5005 to service a request
• CPC Class Codes: G06F 9/5027 the resource being a machine, e.g. CPUs, Servers, Terminals
• CPC Class Codes: G06F 9/5044 considering hardware capabilities

Abstract

An operating system provides instructions for execution by plural hardware threads of a multithreaded core of a processor, the plural hardware threads appearing as separate logical processors to the operating system. An abstraction layer converts respective identifiers of the plural hardware threads to a core identifier representing the core. The abstraction layer presents the core identifier to a user application to hide the plural hardware threads from the user application, and to present the core as a single-threaded core to the user application.

Claims

1. A method comprising:

providing, by an operating system, instructions for execution by plural hardware threads of a multithreaded core of a processor, the plural hardware threads appearing as separate logical processors to the operating system, wherein the multithreaded core comprises a core identifier and the plural hardware threads each comprise a hardware thread identifier;

converting, by an abstraction layer, the hardware thread identifiers corresponding to the plural hardware threads to the core identifier representing the multithreaded core; and

presenting, by the abstraction layer, the core identifier to a user application to hide the plural hardware threads from the user application, and to present the multithreaded core as a single-threaded core to the user application.

2. The method of claim 1, further comprising:

executing instructions of the user application on any one of the plural hardware threads.

3. The method of claim 1, further comprising:

in response to a request from the user application for a topology of the processor, sending the core identifier to the user application instead of the hardware thread identifiers corresponding to the plural hardware threads.

4. The method of claim 3, wherein presenting the core identifier to the user application instead of the hardware thread identifiers corresponding to the plural hardware threads is performed in response to an attribute of the user application being set to a first value, the method further comprising:

detecting that an attribute of a second user application is set to a second value different from the first value;

in response to the detecting, presenting the hardware thread identifiers corresponding to the plural hardware threads to the second user application to enable the second user application to view the plural hardware threads.

5. The method of claim 1, further comprising:

receiving, from the user application, a request for a metric of the multithreaded core;

in response to the request, aggregating respective values of the metric for the plural hardware threads to form an aggregate metric value; and

presenting the aggregate metric value to the user application.

6. The method of claim 1, wherein the processor comprises a second multithreaded core that includes plural hardware threads, the plural hardware threads of the second multithreaded core appearing as separate logical processors to the operating system, the method further comprising:

converting, by the abstraction layer, second hardware identifiers corresponding to the plural hardware threads of the second multithreaded core to a second core identifier representing the second multithreaded core;

presenting, by the abstraction layer, the second core identifier to the user application to hide the plural hardware threads of the second multithreaded core from the user application, and to present the second multithreaded core as a single-threaded core to the user application.

7. The method of claim 1, further comprising:

executing a software thread of a higher priority application on a first hardware thread of the plural hardware threads; and

in response to executing the software thread of the higher priority application on the first hardware thread, disabling a second hardware thread of the plural hardware threads to prevent the second hardware thread from executing a software thread of a lower priority application.

8. The method of claim 1, wherein a first hardware thread of the plural hardware threads has a higher priority than a second hardware thread of the plural hardware threads, the first hardware thread consuming more resources of the core than the second hardware thread.

9. The method of claim 8, further comprising:

scheduling instructions to run on the second hardware thread in response to a stall occurring during execution of instructions by the first hardware thread, wherein the second hardware thread is prevented from execute instructions when the first hardware thread is actively executing instructions.

10. A system comprising:

a processor comprising a multithreaded core that includes plural of hardware threads, wherein the multithreaded core comprises a core identifier and the plural of hardware threads each comprise a hardware thread identifier;

an operating system, the plural hardware threads appearing as plural logical processors to the operating system; and

an abstraction layer to;

convert the hardware thread identifiers of the plural hardware threads to a core identifier representing the multithreaded core, and

present the core identifier to a user application to hide the plural hardware threads from the user application, and to present the multithreaded core as a single-threaded core to the user application.

11. The system of claim 10, wherein the abstraction layer is part of the operating system.

12. The system of claim 10, wherein the abstraction layer is to:

in response to a request from the user application for a topology of the processor, send the core identifier to the user application instead of the hardware thread identifiers of the plural hardware threads.

13. The system of claim 10, wherein presenting the core identifier to the user application instead of the hardware thread identifiers corresponding to the plural hardware threads is performed in response to an attribute of the user application being set to a first value, and wherein the abstraction layer is to further:

detect that an attribute of a second user application is set to a second value different from the first value;

in response to the detecting, present the hardware thread identifiers corresponding to the plural hardware threads to the second user application to enable the second user application to view the plural hardware threads.

14. The system of claim 10, wherein the abstraction layer is to:

receive, from the user application, a request for a metric of the multithreaded core;

in response to the request, aggregate respective values of the metric for the plural hardware threads to form an aggregate metric value; and

present the aggregate metric value to the user application.

15. The system of claim 10, wherein the processor comprises a second multithreaded core that includes plural hardware threads, the plural hardware threads of the second multithreaded core appearing as plural logical processors to the operating system, wherein the abstraction layer is to further:

convert second hardware thread identifiers corresponding to the plural hardware threads of the second multithreaded core to a second core identifier representing the second multithreaded core;

present the second core identifier to the user application to hide the plural hardware threads of the second multithreaded core from the user application, and to present the second multithreaded core as a single-threaded core to the user application.

16. The system of claim 10, wherein a first hardware thread of the plural hardware threads is to execute a software thread of a higher priority application on, and wherein the operating system is to, in response to executing the software thread of the higher priority application on the first hardware thread, disable a second hardware thread of the plural hardware threads to prevent the second hardware thread from executing a software thread of a lower priority application.

17. A non-transitory machine-readable storage medium storing program code that upon execution cause a system to:

provide, by an operating system, instructions for execution by plural hardware threads of a multithreaded core of a processor, the plural hardware threads appearing as separate logical processors to the operating system, wherein the multithreaded core comprises a core identifier and the plural hardware threads each comprise a hardware thread identifier;

convert, by an abstraction layer, the hardware thread identifiers corresponding to the plural hardware threads to a core identifier representing the core; and

present, by the abstraction layer, the core identifier to a user application to hide the plural hardware threads from the user application, and to present the multithreaded core as a single-threaded core to the user application.

18. The non-transitory machine-readable storage medium of claim 17, wherein the program code upon execution cause the system to further:

in response to a request from the user application for a topology of the processor, send the core identifier to the user application instead of the hardware thread identifiers of the plural hardware threads.

19. The non-transitory machine-readable storage medium of claim 17, wherein the program code upon execution cause the system to further:

receive, from the user application, a request for a metric of the core;

in response to the request, aggregate respective values of the metric for the plural hardware threads to form an aggregate metric value; and

present the aggregate metric value to the user application.