System and method for accumulating soft information in LDPC decoding

• US 9,454,414 B2
• Filed: 03/14/2014
• Issued: 09/27/2016
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Microsemi Storage Solutions, Inc (Microchip Technology Incorporated)
• Original Assignee: Microsemi Storage Solutions, Inc (Microchip Technology Incorporated)
• Inventors: Micheloni, Rino, Marelli, Alessia, Onufryk, Peter Z., Norrie, Christopher I. W., Jaser, Ihab, Crippa, Luca
• Primary Examiner(s): Knapp, Justin R
• Application Number:
  US14/210,971
• Publication Number:
  US 20140281828A1
• Time in Patent Office: 928 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: H03M 13/1111 Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
• CPC Class Codes: H03M 13/3769 using symbol combining, e.g. Chase combining of symbols received twice or more

Abstract

A system and method reading, accumulating and processing soft information for use in LDPC decoding. In accordance with the present invention, an LDPC decoder includes accumulation circuitry to receive soft reads of a cell of the nonvolatile memory storage module and to produce an accumulated soft read that can be used to identify an appropriate LLR for the cell. The accumulation circuitry of the present invention may include, an accumulation RAM, an arithmetic logic unit (ALU) and a soft accumulation control and sequencing module for accumulating and processing soft information for use in LDPC decoding.

Claims

1. A method of accumulating soft information of a nonvolatile memory storage module for use in LDPC (Low-Density Party Check) decoding of a codeword stored in the nonvolatile memory storage module, the method comprising:

performing a plurality of reads of a cell of a nonvolatile memory storage module to generate a plurality of soft reads associated with a bit stored in the cell;

accumulating the plurality of soft reads by summing the number of soft reads having a particular logical value to generate an accumulated soft read associated with the bit stored in the cell, wherein the accumulated soft read has a numerical value equal to the sum of the number of soft reads having a particular logical value; and

converting the accumulated soft read into a log-likelihood ratio (LLR) for use in LDPC decoding of a codeword stored in the nonvolatile memory storage module.

2. The method of claim 1, wherein performing a plurality of reads of a cell of a nonvolatile memory storage module to generate a plurality of soft reads associated with a bit stored in the cell further comprises, performing each read of the plurality of soft reads of the cell using a different threshold voltage.

3. The method of claim 1, wherein each of the reads of the plurality of soft reads is representative of a logical “

1”

or a logical “

0” and

accumulating the plurality of soft reads by summing the number of soft reads having a particular logical value to generate an accumulated soft read associated with the bit stored in the cell further comprises, summing the soft reads representative of a logical “

1”

to generate the accumulated soft read associated with the bit stored in the cell, wherein the accumulated soft read associated with the bit stored in the cell comprises a single numerical value.

4. The method of claim 1, further comprising, after performing a plurality of reads of a cell of a nonvolatile memory storage module to generate a plurality of soft reads associated with a bit stored in the cell further comprises, compressing the plurality of soft reads, the summing the number of soft reads having a particular logical value generating a compressed soft read comprising a single numerical value, wherein the single numerical value is represented by a plurality of bits.

5. The method of claim 4, wherein performing a plurality of reads of a cell of a nonvolatile memory storage module to generate a plurality of soft reads associated with a bit stored in the cell further comprises, performing each of the soft reads of the plurality of soft reads of the cell using a different threshold voltage.

6. The method of claim 4, wherein each of the soft reads in the plurality of soft reads is representative of a logical “

1”

or a logical “

0” and

wherein summing the number of soft reads having a particular logical value to identify a single numerical value associated with the bit stored in the cell further comprises, summing the plurality of soft reads representative of a logical “

1”

to generate the single numerical value associated with the bit stored in the cell.

7. The method of claim 4, further comprising sending to a nonvolatile memory controller a first page that includes one of the bits in the plurality of bits;

and

sending to the nonvolatile memory controller one or more additional pages, each of the additional pages including one of the bits in the plurality of bits, until all of the bits in the plurality of bits have been sent to the nonvolatile memory controller;

wherein the accumulating the plurality of soft reads further comprises receiving the first page and the one or more additional pages at the nonvolatile memory controller; and

concatenating the bits of the plurality of bits in the first page and the one or more additional pages to generate the accumulated soft read associated with the bits stored in the cell.

8. The method of claim 1, wherein performing a plurality of reads of a cell of a nonvolatile memory storage module to generate a plurality of soft reads associated with a bit stored in the cell further comprises, performing one or more reads of one or more neighboring cells of the cell of the nonvolatile memory storage module to generate one or more neighboring cell soft reads associated with a bit stored in the one or more neighboring cells.

9. The method of claim 8, wherein performing one or more reads of the one or more neighboring cells of the cell of the nonvolatile memory storage module to generate one or more neighboring cell soft reads associated with a bit stored in the one or more neighboring cells further comprises, performing each of the one or more soft reads of the one or more neighboring cells using a different threshold voltage.

10. The method of claim 8, wherein accumulating the one or more soft reads to generate an accumulated soft read associated with the bit stored in the cell further comprises, concatenating the plurality of soft reads associated with the bit stored in the cell and the one or more neighboring cell soft reads associated with the bit stored in the one or more neighboring cells.

11. A nonvolatile memory controller for accumulating soft information of a nonvolatile memory storage module for use in LDPC (Low-Density Parity Check) decoding of a codeword stored in the nonvolatile memory storage module, the nonvolatile memory controller comprising:

read circuitry configured for performing a plurality of reads of a cell of a nonvolatile memory storage module to generate a plurality of soft reads associated with a bit stored in the cell;

accumulation circuitry coupled to the read circuitry, the accumulation circuitry configured for accumulating the plurality of soft reads to generate an accumulated soft read associated with the bit stored in the cell, wherein the accumulated soft read has a numerical value equal to the sum of the number of soft reads having a particular logical value; and

look-up circuitry coupled to the accumulation circuitry, the look-up circuitry configured for converting the accumulated soft read into a log-likelihood ratio (LLR) for use in LDPC decoding of a codeword stored in the nonvolatile memory storage module.

12. The nonvolatile memory controller of claim 11, wherein the read circuitry is further configured for performing each read of the plurality of reads of the cell using a different threshold voltage.

13. The nonvolatile memory controller of claim 11, wherein each of the reads of the plurality of reads is representative of a logical “

1”

or a logical “

0” and

wherein the accumulation circuitry is further configured for summing the soft reads representative of a logical “

1”

to generate the accumulated soft read associated with the bit stored in the cell.

14. The nonvolatile memory controller of claim 11, wherein the nonvolatile memory storage module comprises read circuitry configured for performing the plurality of reads of a cell of a nonvolatile memory storage module to generate the plurality of soft reads associated with a bit stored in the cell and the nonvolatile memory storage module further comprises compression circuitry for compressing the plurality of soft reads by summing the number of soft reads having a particular logical value to generate a compressed soft read having the numerical value, wherein the numerical value is represented by a plurality of bits.

15. The nonvolatile memory controller of claim 14, wherein each of the reads of the plurality of soft reads is representative of a logical “

1”

or a logical “

0” and

wherein the compression circuitry is further configured for summing the plurality of soft reads representative of a logical “

1”

to generate the compressed soft read.

16. The nonvolatile memory controller of claim 14, wherein the accumulation circuitry is further configured for concatenating the plurality of soft reads associated with the bit stored in the cell and the one or more neighboring cell soft reads associated with the bit stored in the one or more neighboring cells to generate the accumulated soft read associated with the bits stored in the cell.

17. The nonvolatile memory controller of claim 11, wherein the read circuitry is further configured for performing one or more reads of one or more neighboring cells of the cell of the nonvolatile memory storage module to generate one or more neighboring cell soft reads associated with a bit stored in the one or more neighboring cells.

18. The nonvolatile memory controller of claim 11, further comprising one or more LLR look-up tables associated with the nonvolatile memory storage module.

19. A system for accumulating soft information for use in LDPC (Low-Density Parity Check) decoding, the system comprising:

a nonvolatile memory storage module storing a codeword;

read circuitry coupled to the nonvolatile memory storage module, the read circuitry configured for performing a plurality of reads of a cell of the nonvolatile memory storage module to generate a plurality of soft reads associated with a bit stored in the cell;

accumulation circuitry coupled to the read circuitry, the accumulation circuitry configured for accumulating the plurality of soft reads to generate an accumulated soft read associated with the bit stored in the cell, wherein the accumulated soft read has a numerical value equal to the sum of the number of soft reads having a particular logical value; and

look-up circuitry coupled to the accumulation circuitry, the look-up circuitry for converting the accumulated soft read into a log-likelihood ratio (LLR) for use in LDPC decoding of the codeword stored in the nonvolatile memory storage module.

20. The system of claim 19 further comprising:

a nonvolatile memory controller;

compression circuitry for compressing the plurality of soft reads by summing the number of soft reads having a particular logical value to generate a compressed soft read consisting of the numerical value, wherein the numerical value is represented by a plurality of bits, the compression circuitry configured for sending to the nonvolatile memory controller a first page that includes one of the bits in the plurality of bits and one or more additional pages, each of the additional pages including one of the bits in the plurality of bits, until all of the bits in the plurality of bits have been sent to the nonvolatile memory controller; and

wherein the nonvolatile memory controller is further configured for receiving the first page and the one or more additional pages and concatenating the bits of the plurality of bits in the first page and the one or more additional pages to generate the accumulated soft read associated with the bits stored in the cell.