Sharing local cache from a failover node

• US 9,454,485 B2
• Filed: 08/01/2013
• Issued: 09/27/2016
• Est. Priority Date: 08/01/2013
• Status: Active Grant

• Current Assignee: Lenovo International Limited (Lenovo Group Ltd.)
• Original Assignee: Lenovo Enterprise Solutions (Singapore) Pte., Ltd. (Lenovo Group Ltd.)
• Inventors: Cudak, Gary D., Do, Lydia M., Hardee, Christopher J., Roberts, Adam
• Primary Examiner(s): CHOE, YONG J
• Application Number:
  US13/956,596
• Publication Number:
  US 20150039834A1
• Time in Patent Office: 1,153 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/2025 using centralised failover control functionality
• CPC Class Codes: G06F 11/2038 with a single idle spare processing component
• CPC Class Codes: G06F 11/2043 where the redundant components share a common memory address space
• CPC Class Codes: G06F 11/2046 where the redundant components share persistent storage G06F11/2043 takes precedence
• CPC Class Codes: G06F 11/2097 maintaining the standby controller/processing unit updated initialisation or re-synchronisation thereof G06F11/1658 and subgroups
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0871 Allocation or management of cache space
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/286 Mirrored cache memory
• CPC Class Codes: G06F 2212/311 In host system

Abstract

Sharing local cache from a failover node, including: determining, by a managing compute node, whether a first compute node and a second compute node each have a local cache, where the second compute node is a mirrored copy of the first compute node; responsive to determining that the first compute node and the second compute node each have a local cache, combining, by the managing compute node, local cache on the first compute node and local cache on the second compute node into unified logical cache; receiving, by the managing compute node, a memory access request; and sending, by the managing compute node, the memory access request to an appropriate local cache in the unified logical cache.

Claims

1. An apparatus comprising a computer processor and a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the steps of:

determining whether a first compute node and a failover compute node each have an internal cache, wherein the failover compute node is functioning as a mirrored copy of the first compute node;

responsive to determining that the first compute node and the failover compute node each have an internal cache, combining into a unified logical cache, a first internal cache of the first compute node and a second internal cache of the failover compute node;

receiving a memory access request; and

sending the memory access request to one of the internal caches in the unified logical cache including;

determining whether the first internal cache includes data requested by the memory access request;

responsive to determining that the first internal cache does not include data requested by the memory access request, determining whether the second internal cache includes data requested by the memory access request; and

responsive to determining that the second internal cache does include data requested by the memory access request, sending the memory access request to the failover compute node.

2. The apparatus of claim 1 wherein the memory access request includes a memory address specifying a location in memory to read data from.

3. A computer program product including a non-transitory computer readable storage medium, the computer program product comprising computer program instructions that, when executed, cause a computer to carry out the steps of:

determining whether a first compute node and a failover compute node each have an internal cache, wherein the failover compute node is functioning as a mirrored copy of the first compute node;

responsive to determining that the first compute node and the failover compute node each have an internal cache, combining into a unified logical cache, a first internal cache of the first compute node and a second internal cache of the failover compute node;

receiving a memory access request; and

sending the memory access request to one of the internal caches in the unified logical cache including;

determining whether the first internal cache includes data requested by the memory access request;

responsive to determining that the first internal cache does not include data requested by the memory access request, determining whether the second internal cache includes data requested by the memory access request; and

responsive to determining that the second internal cache does include data requested by the memory access request, sending the memory access request to the failover compute node.

4. The computer program product of claim 3 wherein the memory access request includes a memory address specifying a location in memory to read data from.