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Methods, systems, and computer program product for an integrated circuit package design estimator

  • US 9,454,634 B1
  • Filed: 12/31/2014
  • Issued: 09/27/2016
  • Est. Priority Date: 12/31/2014
  • Status: Active Grant
First Claim
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1. A computer implemented method for implementing an IC package design with an integrated circuit package design estimator, comprising:

  • determining an estimated number of layers for an integrated circuit (IC) package design that includes one or more IC die designs with a layer and stack-up estimation mechanism comprising at least one processor that identifies the IC package design and determines the estimated number of layers for the IC package design;

    determining whether the estimated number of layers suffice to accommodate routing demands for interconnections between the IC package design and the one or more IC die designs with the layer and stack-up estimation mechanism;

    determining a power layer or a ground layer based in part or in whole upon one or more factors with a power and ground plane estimation mechanism; and

    generating an output for the IC package design with a guideline and scheme generation mechanism that functions in conjunction with the at least one processor that generates the output with at least the estimated number of layers and the power layer or the ground layer.

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