Methods, systems, and computer program product for an integrated circuit package design estimator

• US 9,454,634 B1
• Filed: 12/31/2014
• Issued: 09/27/2016
• Est. Priority Date: 12/31/2014
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Singh, Surender, Singh, Avinash, Kukal, Taranjit Singh
• Primary Examiner(s): Parihar, Suchin
• Application Number:
  US14/588,279
• Time in Patent Office: 636 Days
• Field of Search: 716/127
• US Class Current: 1/1
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Disclosed are mechanisms for implementing an IC package layout design with an integrated circuit package design estimator. These mechanisms determine an estimated number of layers for an integrated circuit (IC) package design including one or more IC die designs, determine whether the estimated number of layers suffice to accommodate routing demands for the IC package layout design, determine a power layer and/or a ground layer based in part or in whole upon one or more factors, and generate an output for the IC package layout design based using at least the estimated number of layers and the power layer and/or the ground layer. These mechanisms use input including connectivity information, thermal effects, and/or IC placement information to determine estimates for the total number of layers, layer stack-up, power and ground plane assignment, and via libraries to guide IC package layout design.

Claims

1. A computer implemented method for implementing an IC package design with an integrated circuit package design estimator, comprising:

determining an estimated number of layers for an integrated circuit (IC) package design that includes one or more IC die designs with a layer and stack-up estimation mechanism comprising at least one processor that identifies the IC package design and determines the estimated number of layers for the IC package design;

determining whether the estimated number of layers suffice to accommodate routing demands for interconnections between the IC package design and the one or more IC die designs with the layer and stack-up estimation mechanism;

determining a power layer or a ground layer based in part or in whole upon one or more factors with a power and ground plane estimation mechanism; and

generating an output for the IC package design with a guideline and scheme generation mechanism that functions in conjunction with the at least one processor that generates the output with at least the estimated number of layers and the power layer or the ground layer.

2. The computer implemented method of claim 1, wherein the layer and stack-up estimation mechanism that determines the estimated number of layers further performs acts comprising:

determining an estimated number of layers for the IC package design;

identifying one or more fan-out inputs; and

invoking a prioritization mechanism to determine a set of priorities of routing direction for a fan-out pin of a plurality of fan-out pins of an IC die design of the one or more IC die designs in the IC package design.

3. The computer implemented method of claim 2, wherein the one or more fan-out inputs include a netlist of the IC package design, geometric information of the IC package design, placement data for at least one of the one or more IC die designs, or information about power supplies to the IC package design.

4. The computer implemented method of claim 2, wherein the layer and stack-up estimation mechanism that determines the estimated number of layers further performs the acts comprising:

determining a set of characteristics upon which the estimated number of layers depends;

determining a relation between the estimated number of layers and the set of characteristics; and

determining the estimated number of layers for the IC package design using the relation.

5. The computer implemented method of claim 2, wherein the layer and stack-up estimation mechanism that determines the estimated number of layers further performs the acts comprising:

invoking a fan-out sequence estimation mechanism to determine a fan-out sequence for fanning out the plurality of fan-out pins;

invoking a trace estimation mechanism or a trace path estimation mechanism to determine an estimated number of traces between two fan-out pins based in part or in whole upon one or more criteria; and

determining a plurality of trace paths based in part or in whole upon the set of priorities with the trace path estimation mechanism or the trace estimation mechanism.

6. The computer implemented method of claim 5, wherein the one or more criteria comprise one or more design rules and/or one or more characteristics of the IC die design, and the one or more characteristics include a total number of nets.

7. The computer implemented method of claim 5, wherein the layer and stack-up estimation mechanism that determines the estimated number of layers further performs the acts comprising:

incrementing or decrementing the estimated number of layers for the IC package design.

8. The computer implemented method of claim 2, wherein the prioritization mechanism that determines the set of priorities of routing direction further performs the acts comprising:

identifying the fan-out pin from the plurality of fan-out pins of the IC die design;

partitioning the IC die design into a plurality of partitions; and

identifying a position of the fan-out pin in the IC die design.

9. The computer implemented method of claim 8, wherein the prioritization mechanism that determines the set of priorities of routing direction further performs the acts comprising:

identifying a destination for the fan-out pin; and

determining or updating the set of priorities of routing direction using the destination as a guide.

10. The computer implemented method of claim 5, wherein the fan-out sequence estimation mechanism that determines the fan-out sequence further performs the acts comprising:

identifying one or more fan-out pins of the plurality of fan-out pins;

identifying a default sequence for fanning out the IC die design;

identifying one or more sets of priorities of routing direction for the one or more fan-out pins; and

identifying one or more corresponding destinations for the one or more fan-out pins.

11. The computer implemented method of claim 10, wherein the fan-out sequence estimation mechanism that determines the fan-out sequence further performs the acts comprising:

determining whether potential routing for the one or more fan-out pins conflicts with one or more remaining fan-out pins of the IC die design;

identifying one or more other fan-out pins exhibiting similar priorities as the one or more fan-out pins and one or more corresponding sets of priorities of routing direction for the one or more remaining fan-out pins; and

modifying the default sequence for at least some of the plurality of fan-out pins that correspond to the one or more sets of priorities and the one or more corresponding sets of priorities.

12. The computer implemented method of claim 5, wherein the trace estimation mechanism or the trace path estimation mechanism that determines the estimated number of traces further performs the acts comprising:

invoking a partitioning mechanism to partition the IC design into multiple blocks;

identifying a block from the multiple blocks;

identifying one or more design rules and/or routing requirements; and

determining the estimated number of traces based in part or in whole upon the one or more design rules and/or the routing requirements with the trace estimation mechanism.

13. The computer implemented method of claim 5, wherein the trace path estimation mechanism or the trace path estimation mechanism that determines the plurality of trace paths further performs the acts comprising:

identifying the fan-out pin of the IC die design as a starting point for a search for viable routing solutions;

identifying the set of priorities of routing direction for the fan-out pin; and

determining a partitioning scheme dividing the IC die design into a set of blocks.

14. The computer implemented method of claim 13, wherein the trace path estimation mechanism or the trace path estimation mechanism that determines the plurality of trace paths further performs the acts comprising:

identifying a routing direction from the set of priorities of routing direction and one or more blocks from the set of blocks based in part or in whole upon the routing direction;

identifying one or more blocks having routing capacity for the pan-out pin from the set of blocks based in part upon the routing direction; and

forming a path by continuing the search in the routing direction until a stopping criterion is reached.

15. The computer implemented method of claim 13, wherein the trace path estimation mechanism or the trace path estimation mechanism that determines the plurality of trace paths further performs the acts comprising:

identifying one or more repetitive or unneeded blocks;

removing the one or more repetitive or unneeded blocks;

determining a total number of blocks along the path; and

determining whether or not the fan-out pin is pushed back into the fan-out sequence based in part upon the total number of blocks.

16. The computer implemented method of claim 1, wherein the power and ground plane estimation mechanism that determines the power layer and/or the ground layer further performs the acts comprising:

identifying power pins of a power net in the IC package design;

grouping at least some of the power pins into a first grouping in a power domain;

identifying thermal effects, data, and/or requirements; and

determining a number of power planes based in part or in whole upon the thermal effects, data, and/or requirements and results of grouping at least some of the power pins.

18. The system of claim 11, wherein the non-transitory memory holds the program code, and the program code includes further instructions that, when executed by the at least one processor or processor core, cause the at least one processor or processor core to determine an estimated number of layers for the IC package design, identify one or more fan-out inputs, and determine a set of priorities of routing direction for a fan-out pin of a plurality of fan-out pins of an IC die design of the one or more IC die designs in the IC package design.

17. A system for implementing an IC package design with an integrated circuit package design estimator, comprising:

one or more mechanisms at least one of which comprises at least one processor or a processor core that executes one or more threads in a computing system;

non-transitory computer accessible storage medium holding program code that includes a sequence of instructions that, when executed by the at least one processor or processor core, cause the at least one processor or processor core to at least determine an estimated number of layers for an integrated circuit (IC) package design that includes one or more IC die designs, determine whether the estimated number of layers suffice to accommodate routing demands for interconnections between the IC package design and the one or more IC die designs, determine a power layer or a ground layer based in part or in whole upon one or more factors, and generate an output for the IC package design based using at least the estimated number of layers and the power layer or the ground layer.

19. An article of manufacture comprising a non-transitory computer accessible storage medium having stored thereupon a sequence of instructions which, when executed by at least one processor or at least one processor core executing one or more threads, causes the at least one processor or the at least one processor core to perform a process for implementing an IC package design with an integrated circuit package design estimator, the process comprising:

determining an estimated number of layers for an integrated circuit (IC) package design that includes one or more IC die designs with a layer and stack-up estimation mechanism comprising at least one processor that identifies the IC package design and determines the estimated number of layers for the IC package design;

determining whether the estimated number of layers suffice to accommodate routing demands for interconnections between the IC package design and the one or more IC die designs with the layer and stack-up estimation mechanism;

determining a power layer or a ground layer based in part or in whole upon one or more factors with a power and ground plane estimation mechanism; and

generating an output for the IC package design with a guideline and scheme generation mechanism that functions in conjunction with the at least one processor that generates the output with at least the estimated number of layers and the power layer or the ground layer.

20. The computer implemented method of claim 19, the process further comprising:

determining an estimated number of layers for the IC package design;

identifying one or more fan-out inputs; and

determining a set of priorities of routing direction for a fan-out pin of a plurality of fan-out pins of an IC die design of the one or more IC die designs in the IC package design.