System and method to trim reference levels in a resistive memory

• US 9,455,013 B2
• Filed: 01/11/2016
• Issued: 09/27/2016
• Est. Priority Date: 09/27/2013
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Kim, Taehyun, Kim, Jung Pill, Kim, Sungryul
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US14/992,753
• Publication Number:
  US 20160125926A1
• Time in Patent Office: 260 Days
• Field of Search: 365/148, 365/158, 365/185.03, 365/222, 365/163, 365/185.11, 365/185.22, 365/185.12, 365/185.18, 365/185.21, 365/185.29, 365/189.011, 365/189.05, 365/154, 365/185.19, 365/185.25, 365/189.15
• US Class Current: 1/1
• CPC Class Codes: G11C 11/15 using multiple magnetic layers G11C11/155 takes precedence
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 2013/0042 Read using differential sensing, e.g. bit line [BL] and bit line bar [BLB]
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

A method includes, at a resistive memory device, determining an average effective reference resistance level based on a first effective reference resistance and a second effective reference resistance. The first effective reference resistance is based on a first set of reference cells of the resistive memory device and the second effective reference resistance is based on a second set of reference cells of the resistive memory device. The method includes trimming a reference resistance at least partially based on the average effective reference resistance level. Trimming the reference resistance includes, in response to determining that the first effective reference resistance is not substantially equal to the average effective reference resistance level, modifying one or more states of one or more magnetic tunnel junction devices associated with the first effective reference resistance.

Claims

1. A method comprising:

at a resistive memory device;

determining an average effective reference resistance level based on a first effective reference resistance and a second effective reference resistance, the first effective references resistance based on a first set of reference cells of the resistive memory device and the second effective reference resistance based on a second set of reference cells of the resistive memory device; and

trimming a reference resistance at least partially based on the average effective reference resistance level, wherein trimming the reference resistance comprises, in response to determining that the first effective reference resistance is not substantially equal to the average effective reference resistance level, modifying one or more states of one or more magnetic tunnel junction devices associated with the first effective reference resistance.

2. The method of claim 1, wherein the one or more states are modified to decrease the first effective reference resistance in response to determining that the first effective reference resistance is greater than the average effective reference resistance level.

3. The method of claim 2, wherein modifying the one or more states comprises increasing a number of magnetic tunnel junction devices of the one or more magnetic tunnel junction devices that are in a parallel state, decreasing a number of magnetic tunnel junction devices of the one or more magnetic tunnel junction devices that are in an antiparallel state, or a combination thereof.

4. The method of claim 1, wherein the one or more states are modified to increase the first effective reference resistance in response to determining that the first effective reference resistance is less than the average effective reference resistance level.

5. The method of claim 4, wherein modifying the one or more states comprises increasing a number of magnetic tunnel junction devices of the one or more magnetic tunnel junction devices that are in an antiparallel state, decreasing a number of magnetic tunnel junction devices of the one or more magnetic tunnel junction devices that are in a parallel state, or a combination thereof.

6. The method of claim 1, further comprising, prior to determining the average effective reference resistance level, initializing a particular reference cell of the first set of reference cells such that a first magnetic tunnel junction device is in a parallel state and a second magnetic tunnel junction device is in an antiparallel state.

7. The method of claim 6, further comprising:

measuring the first effective reference resistance after initializing the particular reference cell; and

measuring the second effective reference resistance.

8. The method of claim 1, wherein the first set of reference cells corresponds to a first word line of the resistive memory device, and wherein the second set of reference cells corresponds to a second word line of the resistive memory device.

9. The method of claim 1, wherein the resistive memory device comprises a magnetoresistive random access memory (MRAM) device, a resistive random access memory (ReRAM) device, a phase change random access memory (PCRAM) device, or any combination thereof.

10. The method of claim 1, wherein trimming the reference resistance is further based on effective reference resistances corresponding to remaining sets of reference cells of the resistive memory device.

11. The method of claim 1, wherein trimming the reference resistance further comprises modifying respective effective reference resistances associated with additional sets of reference cells of the resistive memory device.

12. The method of claim 1, further comprising:

comparing a resistance value associated with a data magnetic tunnel junction device associated with the first set of reference cells to the first effective reference resistance to determine a bit value.

13. The method of claim 1, further comprising measuring the first effective reference resistance, wherein measuring the first effective reference resistance comprises:

setting a resistance value of a variable resistor;

comparing the resistance value to the first effective reference resistance;

in response to determining that the resistance value is greater than or equal to the first effective reference resistance, changing an output, at a sense amplifier of the resistive memory device, from a low voltage to a high voltage; and

in response to determining that the resistance value is less than the first effective reference resistance, sending a control signal to the variable resistor to increment the resistance value.

14. An apparatus comprising:

a resistive memory reference array comprising multiple sets of reference cells;

a reference resistance measurement circuit configured to measure a first effective reference resistance corresponding to a first set of reference cells and to measure a second effective reference resistance corresponding to a second set of reference cells;

a trimming circuit configured to set a reference resistance based on the first effective reference resistance and the second effective reference resistance; and

a write circuit coupled to the trimming circuit, the write circuit configured to modify one or more states of one or more magnetic tunnel junction devices corresponding to the first effective reference resistance in response to a determination that the first effective reference resistance is not substantially equal to an average effective reference resistance corresponding to the multiple sets of reference cells.

15. The apparatus of claim 14, wherein the trimming circuit is further configured to compare the first effective reference resistance to the average effective reference resistance.

16. The apparatus of claim 14, wherein the write circuit is further configured to increase a number of magnetic tunnel junction devices of the one or more magnetic tunnel junction devices that are in a parallel state, decrease a number of magnetic tunnel junction devices of the one or more magnetic tunnel junction devices that are in an antiparallel state, or a combination thereof, in response to a determination that the first effective reference resistance is less than the average effective reference resistance.

17. The apparatus of claim 14, wherein the write circuit is further configured to increase a number of magnetic tunnel junction devices of the one or more magnetic tunnel junction devices that are in an antiparallel state, decrease the number of magnetic tunnel junction devices of the one or more magnetic tunnel junction devices that are in a parallel state, or a combination thereof, in response to a determination that the first effective reference resistance is greater than the average effective reference resistance.

18. The apparatus of claim 14, wherein the write circuit is further configured to selectively modify the first effective reference resistance by changing resistive states corresponding to the first set of reference cells to initialize a first magnetic tunnel junction device in a parallel state and a second magnetic tunnel junction device in an antiparallel state.

19. The apparatus of claim 14, further comprising:

an averaging circuit coupled to the reference resistance measuring circuit, wherein the averaging circuit is configured to receive the first effective reference resistance and the second effective reference resistance from the reference resistance measuring circuit and to compute an average effective reference resistance.

20. The apparatus of claim 14, further comprising a resistive memory data array, wherein the write circuit is configured to selectively write to the resistive memory reference array or to the resistive memory data array.

21. The apparatus of claim 14, further comprising:

a data sense amplifier;

a data cell coupled to a first input of the data sense amplifier; and

a first transfer gate coupled to a second input of the data sense amplifier and to one or more reference cells of the first set of reference cells, wherein the first transfer gate enables the data sense amplifier to determine a bit value of the data cell based on the first effective reference resistance.

22. The apparatus of claim 21, further comprising:

a variable resistor; and

a second transfer gate coupled to the variable resistor and coupled to the second input of the data sense amplifier, wherein the second transfer gate enables the data sense amplifier to determine the bit value of the data cell based on a resistance value corresponding to the variable resistor.

23. The apparatus of claim 14 integrated in at least one semiconductor die.

24. The apparatus of claim 14, further comprising a device selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer, into which the resistive memory reference array, the reference resistance measurement circuit, the write circuit, and the trimming circuit are integrated.

25. An apparatus comprising:

means for storing multiple reference resistance values, the multiple reference resistance values arranged in multiple sets of reference cells;

means for accessing a first set of reference cells to measure a first effective reference resistance corresponding to the first set of reference cells and for accessing a second set of reference cells to measure a second effective reference resistance corresponding to the second set of reference cells;

means for setting a reference resistance based on the first effective reference resistance and the second effective reference resistance; and

means for modifying one or more states of one or more magnetic tunnel junction devices corresponding to the first effective reference resistance in response to a determination by the means for setting that the first effective reference resistance is not substantially equal to an average effective reference resistance corresponding to the multiple sets of reference cells.

26. The apparatus of claim 25 integrated in at least one semiconductor die.

27. The apparatus of claim 25, further comprising a device selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer, into which the means for storing, the means for accessing, the means for setting, and the means for modifying are integrated.

28. A computer readable storage device storing instructions that, when executed by a processor, cause the processor to perform operations comprising:

at resistive memory device;

initiating determining of an average effective reference resistance level based on a first effective reference resistance and a second effective reference resistance, the first effective reference resistance based on a first set of reference cells of the resistive memory device and the second effective reference resistance based on a second set of reference cells of the resistive memory device; and

initiating trimming of a reference resistance at least partially based on the average effective reference resistance level, wherein trimming the reference resistance comprises, in response to determining that the first effective reference resistance is not substantially equal to the average effective reference resistance level, modifying one or more states of one or more magnetic tunnel junction devices associated with the first effective reference resistance.

29. The computer readable storage device of claim 28, wherein the one or more states are modified to decrease the first effective reference resistance in response to determining that the first effective reference resistance is greater than the average effective reference resistance level, and wherein the one or more states are modified to increase the first effective reference resistance in response to determining that the first effective reference resistance is less than the average effective reference resistance level.

30. The computer readable storage device of claim 28, wherein the instructions are executable by a processor integrated in a device selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.