Semiconductor devices and processing methods

• US 9,455,205 B2
• Filed: 10/17/2013
• Issued: 09/27/2016
• Est. Priority Date: 10/09/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Zundel, Markus, Hirler, Franz, Nelle, Peter, Borucki, Ludger, Winkler, Markus, Vogl, Erwin
• Primary Examiner(s): Hollington, Jermele M
• Application Number:
  US14/055,982
• Publication Number:
  US 20140097431A1
• Time in Patent Office: 1,076 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for processing a semiconductor device in accordance with various embodiments may include: providing a semiconductor device having a first pad and a second pad electrically disconnected from the first pad; applying at least one electrical test potential to at least one of the first pad and the second pad; and electrically connecting the first pad and the second pad to one another after applying the at least one electrical test potential.

Claims

1. A method for processing a semiconductor device, comprising:

providing the semiconductor device having a first pad and a second pad electrically disconnected from the first pad;

applying at least one electrical test potential to at least one of the first pad and the second pad; and

electrically connecting the first pad and the second pad to one another after applying the at least one electrical test potential;

wherein the semiconductor device comprises a plurality of device cells, and

wherein the at least one electrical test potential is configured to detect defects in the plurality of device cells.

2. The method of claim 1, wherein the semiconductor device is configured as a trench transistor comprising a source terminal region, a drain terminal region, a gate electrode, and at least one additional electrode disposed at least partially in a trench,

wherein the first pad is coupled to the source terminal region and the second pad is coupled to the at least one additional electrode.

3. The method of claim 2, wherein the at least one additional electrode is configured as a shield electrode.

4. The method of claim 1, wherein electrically connecting the first and second pads to one another comprises depositing an electrically conductive layer over at least a portion of the first and second pads.

5. The method of claim 4, wherein the electrically conductive layer comprises at least one of a metal and a metal alloy.

6. The method of claim 4, wherein the electrically conductive layer has a larger thickness than at least one of the first and second pads.

7. The method of claim 1, wherein the first and second pads are neighboring pads with no electrically conductive element disposed between the first and second pads.

8. The method of claim 1, wherein electrically connecting the first and second pads to one another is carried out in a back end of line processing stage.

9. A semiconductor device, comprising:

at least one device cell comprising at least one trench, at least one first terminal electrode region, at least one second terminal electrode region, at least one gate electrode, and at least one additional electrode disposed at least partially in the at least one trench;

a first pad coupled to the at least one first terminal electrode region;

a second pad coupled to the at least one additional electrode;

an electrically conductive layer disposed over at least a portion of the first pad and the second pad and electrically connecting the first pad to the second pad.

10. A method for processing a semiconductor device, comprising:

providing the semiconductor device having a first pad, a second pad, and a switching element coupled between the first pad and the second pad and switchable between a first state, in which the first and second pads are electrically connected to one another via the switching element, and a second state, in which the first and second pads are not electrically connected to one another via the switching element;

applying at least one electrical test potential to at least one of the first and second pads while the switching element is in the second state; and

switching the switching element from the second state to the first state after applying the at least one electrical test potential to the at least one of the first and second pads.

11. The method of claim 10, wherein providing the semiconductor device comprises providing the semiconductor device with the switching element being in the first state, the method further comprising:

switching the switching element from the first state to the second state before applying the at least one electrical test potential.

12. The method of claim 10, wherein the first state is a resting state of the switching element.

13. The method of claim 10, wherein the switching element is configured as a normally-on transistor.

14. The method of claim 11, wherein switching the switching element from the first state to the second state comprises applying a control voltage to a control terminal of the switching element, and wherein switching the switching element from the second state to the first state comprises turning off application of the control voltage.

15. A semiconductor device, comprising:

at least one device cell comprising at least one trench, at least one first terminal electrode region, at least one second terminal electrode region, at least one gate electrode, and at least one additional electrode disposed at least partially in the at least one trench;

a first pad coupled to the at least one first terminal electrode region;

a second pad coupled to the at least one additional electrode;

a switching element electrically coupled between the first pad and the second pad and switchable between a first state, in which the first and second pads are electrically connected to one another via the switching element, and a second state, in which the first and second pads are electrically disconnected from one another.

16. The semiconductor device of claim 15, wherein the first state is a resting state of the switching element.

17. The semiconductor device of claim 15, wherein the switching element is a normally-on transistor.

18. The semiconductor device of claim 17, further comprising an additional pad coupled to a gate electrode of the normally-on transistor.

19. The semiconductor device of claim 17, further comprising a high-ohmic electrical connection coupling the first pad to a gate electrode of the normally-on transistor.

20. The semiconductor device of claim 19, wherein the high-ohmic electrical connection comprises a meandering trench structure.

21. The semiconductor device of claim 17, wherein the normally-on transistor has a higher breakdown voltage than a transistor formed from the at least one device cell.

22. The semiconductor device of claim 17, wherein a layout of the normally-on transistor is rotated by an angle compared to a layout of a transistor formed from the at least one device cell.