Semiconductor device allowing metal layer routing formed directly under metal pad

• US 9,455,226 B2
• Filed: 01/28/2014
• Issued: 09/27/2016
• Est. Priority Date: 02/01/2013
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Chen, Chun-Liang, Chang, Tien-Chang, Lin, Chien-Chih
• Primary Examiner(s): Tobergte, Nicholas
• Application Number:
  US14/165,594
• Publication Number:
  US 20140217601A1
• Time in Patent Office: 973 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05025 the internal layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05085 with additional elements, e.g. vias arrays, interposed between the stacked layers
• CPC Class Codes: H01L 2224/05096 Uniform arrangement, i.e. array
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

The present invention provides a semiconductor device. The semiconductor device comprises: a metal pad and a first specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device. The first specific metal layer routing is formed on a second metal layer of the semiconductor device, and directly under the metal pad.

Claims

1. A semiconductor device, comprising:

a metal pad, positioned inside a first metal layer of the semiconductor device; and

a first specific metal layer routing, formed on a second metal layer of the semiconductor device, and directly under the metal pad.

2. The semiconductor device of claim 1, wherein the metal pad has a thickness smaller than 20 KA.

3. The semiconductor device of claim 1, wherein material of the metal pad is aluminum.

4. The semiconductor device of claim 1, wherein the first specific metal layer routing has a uniform pattern.

5. The semiconductor device of claim 4, wherein the uniform pattern has a metal density range between 30% and 70%.

6. The semiconductor device of claim 1, wherein the first specific metal layer routing comprises a plurality of first power lines.

7. The semiconductor device of claim 6, wherein there are oxide regions between the first power lines, and each oxide region has a width greater than 2 micrometers.

8. The semiconductor device of claim 1, wherein the first specific metal layer routing comprises a plurality of first ground lines.

9. The semiconductor device of claim 8, wherein there are oxide regions between the first ground lines, and each oxide region has a width greater than 2 micrometers.

10. The semiconductor device of claim 1, wherein the first specific metal layer routing comprises a plurality of first input/output (IO) routing lines.

11. The semiconductor device of claim 10, wherein there are oxide regions between the first IO routing lines, and each oxide region has a width greater than 2 micrometers.

12. The semiconductor device of claim 1, further comprising:

a second specific metal layer routing, formed on the second metal layer of the semiconductor device and connected to the first specific metal layer routing, wherein the second specific metal layer routing is not directly positioned under the metal pad.

13. The semiconductor device of claim 11, wherein the second specific metal layer routing comprises a second power line.

14. The semiconductor device of claim 11, wherein the second specific metal layer routing comprises a second ground line.

15. The semiconductor device of claim 11, wherein the second specific metal layer routing comprises a plurality of second input/output (IO) routing lines.

16. The semiconductor device of claim 1, wherein the semiconductor device is a chip.

17. The semiconductor device of claim 1, wherein the first metal layer and the second metal layer are adjacent metal layers of the semiconductor device.

18. The semiconductor device of claim 6, wherein the first specific metal layer routing comprises at least one unused metal line kept as a dummy pattern.

19. The semiconductor device of claim 10, wherein the first specific metal layer routing comprises at least one unused metal line kept as a dummy pattern.

20. The semiconductor device of claim 15, wherein the second input/output (IO) routing lines have at least a via plug for connecting to another metal layer.