Planar srfet using no additional masks and layout method

• US 9,455,249 B2
• Filed: 08/13/2014
• Issued: 09/27/2016
• Est. Priority Date: 08/13/2014
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bhalla, Anup
• Primary Examiner(s): Vu, David
• Assistant Examiner(s): FOX, BRANDON C
• Application Number:
  US14/458,407
• Publication Number:
  US 20160049392A1
• Time in Patent Office: 776 Days
• Field of Search: 257/330, 257/341
• US Class Current: 1/1
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0727 in combination with diodes, or capacitors or resistors
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

A semiconductor power device is supported on a semiconductor substrate of a first conductivity type with a bottom layer functioning as a bottom electrode and an epitaxial layer overlying the bottom layer with a same conductivity type as the bottom layer. The semiconductor power device includes a plurality of FET cells and each cell further includes a body region of a second conductivity type extending from a top surface into the epitaxial layer. The body region encompasses a heavy body dopant region of second conductivity type. An insulated gate is disposed on the top surface of the epitaxial layer, overlapping a first portion of the body region. A barrier control layer is disposed on the top surface of the epitaxial layer next to the body region away from the insulated gate. A conductive layer overlies the top surface of the epitaxial layer covering a second portion of the body region and the heavy body dopant region extending over the barrier control layer forming a Schottky junction diode.

Claims

1. A semiconductor power device comprising an active cell area having a plurality of power transistor cells supported on a semiconductor substrate, wherein:

each of said power transistor cells comprising a planar insulated gate laterally extending and overlapping a portion of a body region encompassing a heavily doped body region of same conductivity type therein;

the heavily doped body region having a body dopant concentration higher than the body region and extends from a top surface of the substrate into the body region and away from an outer edge of the body region distant from the planar insulated gate;

wherein a Schottky junction barrier metal overlaying a space between adjacent body regions forming a Schottky diode there-in-between wherein the plurality power transistor cells are configured to surround and sharing the space between the adjacent body region as an integrated and shared Schottky diode substantially enclosed by the body regions of the plurality of power transistors.

2. The semiconductor power device of claim 1 wherein:

said body region further encompassing a source region of opposite conductivity type partially overlapping the insulated gate and adjacent to the heavily doped body region.

3. The semiconductor power device of claim 1 further comprising:

a Schottky barrier height adjustment layer on a top portion of the semiconductor substrate in the space between adjacent body regions.

4. The semiconductor power device of claim 1 wherein:

the space between two of the body regions adjacent to each other is narrower than a space between corresponding heavily doped body regions encompassed in the adjacent body regions.

5. The semiconductor power device of claim 1 wherein:

said power transistor cells further comprising MOSFET transistor cells with said heavily doped body regions surrounding the integrated and shared Schottky diode forming a Junction Barrier Controlled Schottky (JBS).

6. The semiconductor power device of claim 5 wherein:

each of said heavily doped body regions is surrounded by a portion of a lightly doped body region between the outer edge of the body region and an outer edge of the heavily doped body region thus improving a breakdown of the JBS.

7. The semiconductor power device of claim 1 wherein:

said semiconductor substrate comprises an epitaxial layer on an upper portion having a gradually increasing dopant concentration along a downward vertical direction thus having a lighter dopant concentration near a top surface of said epitaxial layer.

8. The semiconductor power device of claim 2 wherein:

said body regions are disposed in an upper source dopant layer on top of a lower source dopant layer in said semiconductor substrate and wherein said upper source dopant layer having a smaller dopant concentration than said lower source dopant layer, said upper source dopant layer extends in said substrate to a depth deeper than said heavy body region.

9. The semiconductor power device of claim 8 wherein:

said upper source dopant layer with said smaller source dopant concentration than said lower source dopant layer extends in said semiconductor substrate to a depth above a bottom of the body regions of said power transistor cells.

10. The semiconductor power device of claim 2 wherein:

said heavy body region extends deeper than the source region.

11. A semiconductor power device comprising:

an active cell area having a plurality of power transistor cells supported on a semiconductor substrate, each of said power transistor cells comprising an insulated planar gate laterally extending and overlapping a portion of a body region, wherein the body region further encompasses a heavy body region having a body dopant concentration higher than the body region; and

said power transistor cells are configured to surround and substantially enclose a space between the body regions of the transistor cells wherein the space is covered by a Schottky junction barrier metal thus constituting an integrated and shared Schottky diode substantially enclosed by the body regions of the plurality of power transistors.

12. The semiconductor power device of claim 11 wherein:

said body region further encompassing a source region of opposite conductivity type partially overlapping the insulated gate and adjacent to the heavy body region.

13. The semiconductor power device of claim 11 further comprising:

a Schottky barrier height adjustment layer on a top portion of the semiconductor substrate in the space between adjacent body regions.

14. The semiconductor power device of claim 11 wherein:

said power transistor cells further comprising MOSFET transistor cells with said heavily doped body regions surrounding the integrated and shared Schottky diode forming a Junction Barrier Controlled Schottky (JBS).

15. The semiconductor power device of claim 11 wherein:

said semiconductor substrate comprises an epitaxial layer on an upper portion having a gradually increasing dopant concentration along a vertical direction having a lighter dopant concentration near a top surface of said epitaxial layer.

16. The semiconductor power device of claim 12 wherein:

said body regions are disposed in an upper source dopant layer on top of a lower source dopant layer in said semiconductor substrate and wherein said upper source dopant layer having a smaller dopant concentration than said lower source dopant layer, said upper source dopant layer extends in said substrate to a depth deeper than said heavy body region.

17. The semiconductor power device of claim 16 wherein:

said upper source dopant layer with said smaller source dopant concentration than said lower source dopant layer extends in said semiconductor substrate to a depth above a bottom of the body regions of said power transistor cells.

18. The semiconductor power device of claim 12 wherein:

said heavy body region extends deeper than the source region.

19. A semiconductor power device supported on a semiconductor substrate comprising:

an active cell area having a plurality of power transistor cells wherein each of the power transistor cells comprising an insulated planar gate laterally extending and overlapping a portion of a body region, wherein the body region further encompasses a heavy body region having a body dopant concentration higher than the body region;

wherein the power transistors are configured to surround and substantially enclose a space between the body regions of the power transistors;

a Schottky junction barrier metal covering over the space between;

the body regions of the transistor cells thus constituting an integrated and shared Schottky diode substantially enclosed by the body regions shared by the plurality of power transistors surrounding and substantially enclosing the space; and

wherein a gap between the pair of body regions is narrower than a gap between the pair of heavy body regions.

20. The semiconductor power device of claim 19 wherein:

said heavy body region extends deeper than the source region.

21. The semiconductor power device of claim 19 further comprising:

a Schottky barrier height adjustment layer in a central surface area of the semiconductor substrate between the pair of body regions.

22. The semiconductor power device of claim 19 wherein:

said power transistor cells further comprising MOSFET transistor cells with said heavily doped body regions surrounding the integrated and shared Schottky diode forming a Junction Barrier Controlled Schottky (JBS).

23. The semiconductor power device of claim 22 wherein:

each of said heavy body regions being surrounded by a portion of lightly doped body region between an outer edge of the body region and an outer edge of the heavy body region thus improving a breakdown of the JBS.

24. The semiconductor power device of claim 19 wherein:

said semiconductor substrate comprises an epitaxial layer on an upper portion having a gradually increasing dopant concentration along a vertical direction having a lighter dopant concentration near a top surface of said epitaxial layer.

25. The semiconductor power device of claim 19 wherein:

said body regions are disposed in an upper source dopant layer on top of a lower source dopant layer in said semiconductor substrate and wherein said upper source dopant layer having a smaller dopant concentration than said lower source dopant layer, said upper source dopant layer extends in said substrate to a depth deeper than said heavy body region.

26. The semiconductor power device of claim 25 wherein:

said upper source dopant layer with said smaller source dopant concentration than said lower source dopant layer extends in said semiconductor substrate to a depth above a bottom of the body regions of said power transistor cells.