Replacement fin process in SSOI wafer

• US 9,455,274 B2
• Filed: 01/30/2015
• Issued: 09/27/2016
• Est. Priority Date: 01/30/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Doris, Bruce B., He, Hong, Khakifirooz, Ali, Wang, Junli
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): GRAY, AARON J
• Application Number:
  US14/609,574
• Publication Number:
  US 20160225789A1
• Time in Patent Office: 606 Days
• Field of Search: 257/347, 257/369, 257/351, 257/E27.112, 438/199, 438/478, 438/283
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7849 the means being provided under the channel
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of forming replacement fins in a complimentary-metal-oxide-semiconductor (CMOS) device that includes a p-type field effect transistor device (pFET) and an n-type field effect transistor device (nFET) and a CMOS device are described. The method includes forming strained silicon (Si) fins from a strained silicon-on-insulator (SSOI) layer in both an nFET region and a pFET region, forming insulating layers over the strained Si fins, and forming trenches within the insulating layers to expose the strained Si fins in the pFET region only. The method also includes etching the strained Si fins in the pFET region to expose a buried oxide (BOX) layer of the SSOI layer, etching the exposed portions of the BOX layer to expose a bulk substrate, epitaxially growing a Si portion of pFET replacement fins from the bulk substrate, and epitaxially growing silicon germanium (SiGe) portions of the pFET replacement fins on the Si portion of the pFET replacement fins.

Claims

1. A method of forming replacement fins in a complimentary-metal-oxide-semiconductor (CMOS) device that includes a p-type field effect transistor device (pFET) and an n-type field effect transistor device (nFET), the method comprising:

forming strained silicon (Si) fins from a strained silicon-on-insulator (SSOI) layer in both an nFET region and a pFET region;

forming one or more insulating layers over the strained Si fins;

forming trenches within the one or more insulating layers so as to expose the strained Si fins in the pFET region only;

etching the strained Si fins in the pFET region to expose a buried oxide (BOX) layer of the SSOI layer;

etching the exposed portions of the BOX layer to expose a bulk substrate;

epitaxially growing a Si portion of pFET replacement fins from the bulk substrate; and

epitaxially growing silicon germanium (SiGe) portions of the pFET replacement fins on the Si portion of the pFET replacement fins.

2. The method according to claim 1, wherein the forming the trenches includes defining the trenches by a dielectric film fill around the Si fins and the BOX layer.

3. The method according to claim 2, wherein the epitaxially growing the Si portion of the pFET replacement fins includes controlling a size of growth to keep the Si portion of the pFET replacement fins at or below a height of the BOX layer.

4. The method according to claim 3, wherein the epitaxially growing the SiGe portion of the pFET replacement fins includes controlling a size of growth to keep the SiGe portion of the pFET replacement fins a same height as the Si fins in the nFET region.

5. The method according to claim 1, wherein the forming the Si fins includes patterning a spacer material on a hard mask layer above a strained silicon layer and etching the hard mask layer and the strained silicon layer according to a pattern of the spacer material.

6. The method according to claim 1, wherein the etching the Si fins and the BOX layer in the pFET region includes using a lithographic layer and a patterned photoresist layer, the patterned photoresist layer including gaps aligned with the trenches.

7. The method according to claim 1, wherein the etching the Si fins in the pFET region includes retaining the Si fins in the nFET region.

8. The method according to claim 1, wherein the forming the strained Si fins includes forming tensile strained Si fins.

9. The method according to claim 1, wherein the forming the one or more insulating layers includes forming a layer of an organic dielectric layer (ODL) or a silicon-containing antireflection coating (SiARC).