X-Y address type solid state image pickup device and method of producing the same

• US 9,455,293 B2
• Filed: 10/30/2007
• Issued: 09/27/2016
• Est. Priority Date: 07/11/2001
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Suzuki, Ryoji, Mabuchi, Keiji, Mori, Tomonori
• Primary Examiner(s): WOLDEGEORGIS, ERMIAS T
• Application Number:
  US11/981,467
• Publication Number:
  US 20080076202A1
• Time in Patent Office: 3,255 Days
• Field of Search: 257/432, 257/436, 257/347, 257/228, 438/737, 438/738, 438/705, 438/116, 438/70, 438/57, 438/634, 438/29, 438/31, 438/32, 438/72, 438/121
• US Class Current: 1/1
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14623 Optical shielding
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14685 Process for coatings or optical elements
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H01L 31/02164 for shielding light, e.g. light blocking layers, cold shields for infrared detectors
• CPC Class Codes: H01L 31/0232 Optical elements or arrangements associated with the device H01L31/0236 takes precedence; for photovoltaic cells H01L31/054; for photovoltaic modules H02S40/20
• CPC Class Codes: H01L 31/02327 the optical elements being integrated or being directly associated to the device, e.g. back reflectors optical coatings H01L31/0216
• CPC Class Codes: H04N 25/79 Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors

Abstract

In an X-Y address type solid state image pickup device represented by a CMOS image sensor, a back side light reception type pixel structure is adopted in which a wiring layer is provided on one side of a silicon layer including photo-diodes formed therein, and visible light is taken in from the other side of the silicon layer, namely, from the side (back side) opposite to the wiring layer. Wiring can be made without taking a light-receiving surface into account, and the degree of freedom in wiring for the pixels is enhanced.

Claims

1. A method of producing a solid-state image pickup device comprising:

a step of forming an interlayer insulating film on a face side surface of a semiconductor substrate, the face side surface of the semiconductor substrate is opposite to a different surface of the semiconductor substrate;

a step of forming a semiconductor substrate support member on the interlayer insulating film, the interlayer insulating film is between the semiconductor substrate and the substrate support member;

a step of forming an opening through the substrate support member, the opening extends from a surface of the substrate support member to an electrically conductive pad in the interlayer insulating film; and

a step of chemical mechanically polishing the different surface of the semiconductor substrate to expose a back side surface of the semiconductor substrate, the step of forming the opening occurs prior to the step of chemical mechanically polishing the different surface of the semiconductor substrate.

2. A method as set forth in claim 1, further comprising:

a step of forming a light-shielding film, an insulator is between the light-shielding film and the back side surface of the semiconductor substrate.

3. A method as set forth in claim 2, further comprising:

a step of forming a color filter, a passivation film is between the color filter and the light-shielding film.

4. A method as set forth in claim 3, wherein a pixel portion of the semiconductor substrate is configured to convert wavelengths of light into a signal charge.

5. A method as set forth in claim 4, wherein the wavelengths of the light are transmissible through the color filter and into the back side surface of the semiconductor substrate.

6. A method as set forth in claim 4, wherein the wavelengths of the light are transmissible through the back side surface of the semiconductor substrate and into the pixel portion.

7. A method as set forth in claim 4, wherein the pixel portion is configured to convert visible wavelengths of the light into the signal charge.

8. A method as set forth in claim 4, wherein the pixel portion is configured to convert infrared wavelengths of the light into the signal charge.

9. A method as set forth in claim 4, wherein the pixel portion is configured to convert ultraviolet wavelengths of the light into the signal charge.

10. A method as set forth in claim 3, wherein the passivation film is a plasma silicon nitride film.

11. A method as set forth in claim 3, wherein the passivation film is formed by a chemical vapor deposition process.

12. A method as set forth in claim 3, further comprising:

a step of forming a micro-lens, the color filter being between the micro-lens and the passivation film.

13. A method as set forth in claim 2, further comprising:

a step of stepper registration, the light-shielding film is used during the step of stepper registration.

14. A method as set forth in claim 2, wherein the insulator is formed by a chemical vapor deposition process.

15. A method as set forth in claim 2, wherein the light-shielding film is aluminum or tungsten.

16. A method as set forth in claim 1, further comprising:

a step of forming a different substrate support member on the substrate support member.

17. A method as set forth in claim 16, further comprising:

a step of removing a portion of the different substrate support member to expose the electrical conductor.

18. A method as set forth in claim 17, wherein the step of removing the portion of the different substrate support member occurs after the step of chemical mechanically polishing the different surface of the semiconductor substrate.

19. A method as set forth in claim 1, further comprising:

a step of depositing an electrical conductor into the opening.

20. A method as set forth in claim 19, wherein the electrical conductor is a metal.

21. A method as set forth in claim 19, wherein the electrical conductor extends from the surface of the substrate support member to the electrically conductive pad.

22. A method as set forth in claim 19, wherein the step of depositing the electrical conductor into the opening occurs prior to the step of chemical mechanically polishing the different surface of the semiconductor substrate.

23. A method as set forth in claim 1, further comprising:

a step of introducing an impurity into the face side surface of the semiconductor substrate prior to the step of forming the interlayer insulating film.

24. A method as set forth in claim 23, wherein the step of introducing the impurity is an oblique ion implantation of the impurity.

25. A method as set forth in claim 1, wherein a register mark is in the interlayer insulating film prior to the step of chemical mechanically polishing the different surface of the semiconductor substrate.

26. A method as set forth in claim 25, further comprising:

a step of stepper registration, the register mark being used during the step of stepper registration.

27. A method as set forth in claim 25, wherein the register mark is aluminum or tungsten.

28. A method as set forth in claim 1, wherein the electrically conductive pad is in the interlayer insulating film prior to the step of chemical mechanically polishing the different surface of the semiconductor substrate.

29. A method as set forth in claim 1, wherein the substrate support member is a material from a group consisting of glass, silicon, and an organic film.

30. A method as set forth in claim 1, wherein the substrate support member is from the group consisting of glass, silicon, and an organic film.

31. A method as set forth in claim 1, wherein the semiconductor substrate is polished to a thickness of about 10 μ

m to 20 μ

m.

32. A method as set forth in claim 1, wherein the semiconductor substrate is polished to a thickness of about 5 μ

m to 15 μ

m.

33. A method as set forth in claim 1, wherein the semiconductor substrate is polished to a thickness of about 15 μ

m to 50 μ

m.

34. A method as set forth in claim 1, wherein the semiconductor substrate is polished to a thickness of about 3 μ

m to 7 μ

m.