Setting channel voltages of adjustable resistance bit line structures using dummy word lines
First Claim
1. A method for operating a non-volatile memory, comprising:
- determining a first word line within a memory array;
determining a first global bit line within the memory array, the first global bit line is connected to an adjustable resistance bit line structure that includes an adjustable resistance local bit line and a select gate, a first memory cell is arranged between the adjustable resistance local bit line and the first word line;
determining a dummy word line within the memory array, the dummy word line comprises the word line closest to the first global bit line;
determining a dummy word line voltage; and
performing a memory operation on the memory array, the memory operation includes applying a selected word line voltage to the first word line and applying a selected bit line voltage to the first global bit line while the adjustable resistance local bit line is set into a conducting state, the memory operation includes applying the dummy word line voltage to the dummy word line while the adjustable resistance local bit line is set into the conducting state, the adjustable resistance local bit line comprises undoped polysilicon.
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Accused Products
Abstract
Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.
16 Citations
18 Claims
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1. A method for operating a non-volatile memory, comprising:
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determining a first word line within a memory array; determining a first global bit line within the memory array, the first global bit line is connected to an adjustable resistance bit line structure that includes an adjustable resistance local bit line and a select gate, a first memory cell is arranged between the adjustable resistance local bit line and the first word line; determining a dummy word line within the memory array, the dummy word line comprises the word line closest to the first global bit line; determining a dummy word line voltage; and performing a memory operation on the memory array, the memory operation includes applying a selected word line voltage to the first word line and applying a selected bit line voltage to the first global bit line while the adjustable resistance local bit line is set into a conducting state, the memory operation includes applying the dummy word line voltage to the dummy word line while the adjustable resistance local bit line is set into the conducting state, the adjustable resistance local bit line comprises undoped polysilicon. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A non-volatile storage system, comprising:
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a memory array, the memory array includes a first adjustable resistance bit line structure, the first adjustable resistance bit line structure includes an adjustable resistance local bit line and a select gate; and one or more managing circuits in communication with the first adjustable resistance bit line structure, the one or more managing circuits configured to identify a first word line within the memory array, a first memory cell is arranged between the adjustable resistance local bit line and the first word line, the one or more managing circuits configured to identify a first global bit line within the memory array, the first global bit line is connected to the adjustable resistance local bit line, the one or more managing circuits configured to identify a dummy word line within the memory array, the dummy word line comprises the word line closest to the first global bit line, the one or more managing circuits configured to determine a dummy word line voltage, the one or more managing circuits configured to cause the adjustable resistance local bit line to be set into a conducting state during a memory operation, the one or more managing circuits configured to cause a selected word line voltage to be applied to the first word line and a selected bit line voltage to be applied to the first global bit line while the adjustable resistance local bit line is set into the conducting state, the one or more managing circuits configured to cause the dummy word line voltage to be applied to the dummy word line while the adjustable resistance local bit line is set into the conducting state, the adjustable resistance local bit line comprises undoped polysilicon. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A method for operating a non-volatile memory, comprising:
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identifying a dummy word line within a memory array, the memory array includes a first word line and a first global bit line, the first global bit line is connected to an adjustable resistance bit line structure that includes an adjustable resistance local bit line and a select gate, a first memory cell is arranged between the adjustable resistance local bit line and the first word line, the dummy word line comprises the word line closest to the first global bit line; determining a dummy word line voltage; determining a maximum current limit for the first memory cell; determining a selected select gate voltage based on the maximum current limit; and performing a memory operation on the memory array, the memory operation includes applying a selected word line voltage to the first word line and applying a selected bit line voltage to the first global bit line while the adjustable resistance local bit line is set into a conducting state, the memory operation includes applying the dummy word line voltage to the dummy word line while the adjustable resistance local bit line is set into the conducting state, the memory operation includes applying the selected select gate voltage to the select gate during the memory operation such that a current through the first memory cell does not exceed the maximum current limit for the first memory cell, the adjustable resistance local bit line comprises undoped polysilicon. - View Dependent Claims (18)
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Specification