Fin field-effect transistors having controlled fin height

• US 9,455,325 B2
• Filed: 04/22/2015
• Issued: 09/27/2016
• Est. Priority Date: 02/23/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wann, Clement Hsingjen, Yeh, Ling-Yen, Shih, Chi-Yuan, Shao, Yuan-Fu, Guo, Wen-Huei, Lee, Tung Ying
• Primary Examiner(s): DANG, PHUC T
• Application Number:
  US14/692,823
• Publication Number:
  US 20150228743A1
• Time in Patent Office: 524 Days
• Field of Search: 257/368, 257/618, 438/423
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/02 Semiconductor bodies ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 29/06 characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7856 with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides H01L29/7855 takes precedence

Abstract

An apparatus includes a semiconductor substrate having a plurality of fins, wherein the plurality of fins includes a first group of fins and a second group of fins. The apparatus further includes a high fin density area on the semiconductor substrate including a first dielectric between the first group of fins in the high fin density area, said first dielectric having a first dopant concentration. The apparatus further includes a low fin density area on the semiconductor substrate including a second dielectric between the second group of fins in the low fin density area, said second dielectric having a second dopant concentration. The first dielectric and the second dielectric are a same material as deposited and the first dopant concentration and the second dopant concentration are different.

Claims

1. An apparatus comprising:

a semiconductor substrate having a plurality of fins, wherein the plurality of fins includes a first group of fins and a second group of fins;

a high fin density area on the semiconductor substrate including a first dielectric between the first group of fins in the high fin density area, said first dielectric having a first dopant concentration; and

a low fin density area on the semiconductor substrate including a second dielectric between the second group of fins in the low fin density area, said second dielectric having a second dopant concentration;

wherein the first dielectric and the second dielectric are a same material as deposited and the first dopant concentration and the second dopant concentration are different.

2. The apparatus of claim 1, wherein the plurality of fins have a substantially same height.

3. The apparatus of claim 1, wherein fin heights of the plurality of fins have a uniformity of about or greater than 95%.

4. The apparatus of claim 1, wherein the first dopant concentration and the second dopant concentration comprise a concentration of carbon or germanium.

5. The apparatus of claim 1, wherein the first dopant concentration and the second dopant concentration comprise a concentration of arsenic, phosphorous, or boron.

6. An apparatus comprising:

a substrate;

a first plurality of fins having a first pitch in a first region of the substrate;

a second plurality of fins having a second pitch in a second region of the substrate, wherein the second pitch is different from the first pitch; and

a dielectric material between fins of the first plurality of fins and between fins of the second plurality of fins, wherein the dielectric material in the first region has a different dopant concentration from the dielectric material in the second region, and the first region has a different etch rate from the second region.

7. The apparatus of claim 6, wherein at least one of the first plurality of fins or the second plurality of fins is part of a logic device.

8. The apparatus of claim 6, wherein at least one of the first plurality of fins or the second plurality of fins is part of a memory device.

9. The apparatus of claim 6, wherein at least one of the first plurality of fins or the second plurality of fins is part of an input/output device.

10. The apparatus of claim 6, wherein a width of fins of the first plurality of fins is different form a width of fins of the second plurality of fins.

11. The apparatus of claim 6, further comprising a gate electrode over fins of the first plurality of fins.

12. The apparatus of claim 6, wherein a doping concentration tail of the dielectric material in the first region is different from a doping concentration tail of the dielectric material in the second region.

13. The apparatus of claim 6, further comprising a third plurality of fins having a third pitch in a third region of the substrate, wherein the third pitch is different from the first pitch and from the second pitch.

14. The apparatus of claim 13, wherein the dielectric material is between fins of the third plurality of fins, and the dielectric material in the third region has a different dopant concentration from the dopant concentration of the dielectric material in the first region and from the dopant concentration of the dielectric material in the second region.

15. The apparatus of claim 6, wherein the first dopant concentration ranges from about 1E14 atoms/cm² to about 4E15 atoms/cm².

16. An apparatus comprising:

a substrate;

a first plurality of fins having a first pitch in a first region of the substrate;

a second plurality of fins having a second pitch in a second region of the substrate, wherein the second pitch is different from the first pitch; and

a dielectric material between fins of the first plurality of fins and between fins of the second plurality of fins, wherein an etch selectivity of the dielectric material in the first region is different from an etch selectivity of the dielectric material in the second region.

17. The apparatus of claim 16, wherein the dielectric material in the second region is undoped.

18. The apparatus of claim 16, wherein the first pitch is less than the second pitch, and the etch selectivity of the dielectric material in the first region is higher than the etch selectivity of the dielectric material in the second region.

19. The apparatus of claim 16, wherein a top of fins in the first plurality of fins is substantially level with a top of fins in the second plurality of fins.

20. The apparatus of claim 16, wherein the dielectric material comprises a same base material in the first region and in the second region.