Integrated circuit metal gate structure having tapered profile

• US 9,455,344 B2
• Filed: 05/22/2014
• Issued: 09/27/2016
• Est. Priority Date: 08/20/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chuang, Harry-Hak-Lay, Thei, Kong-Beng, Yeh, Chiung-Han, Wu, Ming-Yuan, Liang, Mong-Song
• Primary Examiner(s): Vu, David
• Application Number:
  US14/284,559
• Publication Number:
  US 20140246712A1
• Time in Patent Office: 859 Days
• Field of Search: 438/183, 438/595, 438/596, 438/652, 438/692, 438/700, 438/701, 257/407, 257/412, 257/E21.444, 257/E21.453
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66606 with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology H01L29/66621 takes precedence
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A device having a gate where the profile of the gate provides a first width at a top region and a second width at a bottom region is described. The gate may include tapered sidewalls. The gate may be a metal gate structure.

Claims

1. A semiconductor device, comprising:

a source and a drain region formed on a substrate; and

a gate structure disposed on the substrate between the source and drain regions, the gate structure including;

a gate dielectric layer, wherein the gate dielectric includes a high-k dielectric material; and

a metal gate electrode, wherein the metal gate electrode includes a tapered profile, the tapered profile being defined by a first sidewall and a second opposing sidewall, each of the first and second sidewalls including a first portion substantially perpendicular to a top surface of the substrate and a second portion overlying and oblique to the first portion, the second portion of the first and second sidewalls defining a first width of the metal gate electrode and the first portion defining a second width of the metal gate electrode, the first width greater than the second width and wherein the first and second portion connect at a connection point, and wherein the metal gate electrode includes;

a first conductive layer having a top surface below the connection point; and

a work function metal layer extending from below the connection point to above the connection point;

spacer elements abutting the gate structure, wherein a sidewall of the spacer elements defines the tapered profile; and

a first dielectric layer on the spacer elements having a top surface that extends from one of the spacer elements to an overlying second dielectric layer, wherein the top surface is substantially parallel a top surface of the substrate.

2. The device of claim 1, wherein the second portion is a curved sidewall.

3. The device of claim 1, wherein the first portion is oblique to the top surface of the substrate.

4. The device of claim 1, wherein the second portion of tapered profile includes a tapered angle between approximately 5 and 30 degrees.

5. The device of claim 1, wherein the second portion of the tapered profile includes a tapered angle between approximately 5 and 20 degrees.

6. The device of claim 1, wherein

the first dielectric layer is a contact etch stop layer (CESL) and the second dielectric layer is an inter layer dielectric (ILD).

7. A semiconductor device, comprising:

a metal gate structure disposed on a semiconductor substrate, wherein the metal gate structure has a first region with a first width and a second region underlying the first portion, wherein the second region has a second width, the second width being less than the first width; and

wherein the metal gate structure includes a sidewall having an upper portion that is oblique to and contiguous with a lower portion of the sidewall, the lower portion being substantially perpendicular the semiconductor substrate and wherein the sidewall has a first termination point in the upper portion and a second termination point in the lower portion, the sidewall from the first termination point to the second termination point defined by a spacer element abutting the metal gate structure; and

wherein the metal gate structure includes a work function metal layer and a fill metal layer, wherein the work function metal layer defines the upper portion of the sidewall, and wherein the fill metal layer has sidewalls which are substantially parallel the lower portion of the sidewall of the metal gate structure and extend from an interface with the work function metal layer to a top surface the fill metal layer.

8. The device of claim 7, further comprising:

a contact etch stop layer (CESL) on the spacer element.

9. The device of claim 8, wherein the spacer elements have a top surface that is substantially oblique to the lower portion of the sidewall.

10. The device of claim 8, wherein the CESL has a top surface extending from the spacer element to an overlying layer, the top surface being substantially coplanar with at least one of a top surface of the metal gate structure and a top surface of the overlying layer, the overlying layer being an inter layer dielectric (ILD) layer on the semiconductor substrate.

11. The device of claim 7, wherein the metal gate structure is further comprising:

a high-k dielectric layer, wherein the high-k dielectric layer defines a length of the lower portion of the sidewall of the metal gate structure.

12. The device of claim 7, wherein the upper portion is substantially linear.

13. The device of claim 7, wherein the upper portion is curved.

14. A device, comprising:

a contact etch stop layer (CESL) on the a semiconductor substrate, wherein a top surface of the CESL has a length, an entirety of the length being substantially parallel a top surface of the semiconductor substrate;

a gate structure surrounded by the CESL and having a substantially coplanar top surface with the top surface of the CESL, wherein the gate structure includes a sidewall having an upper portion that is oblique to and directly connected to a lower portion of the sidewall, the lower portion being substantially perpendicular the semiconductor substrate, wherein the gate structure includes a high-k dielectric layer, wherein a top surface of the high-k dielectric layer is planar with a connection of the upper portion and the lower portion of the sidewall.

15. The device of claim 14,

wherein the high dielectric constant (high k) gate dielectric layer on the semiconductor substrate defines the lower portion of the gate structure sidewall.

16. The device of claim 14, further comprising:

an interlayer dielectric (ILD) layer on and around the CESL.

17. The device of claim 16, wherein the top surface having the length extends from the ILD layer to a spacer element abutting the gate structure, and wherein the ILD layer has a top surface substantially coplanar with the top surface of the CESL that has the length that extends from the ILD layer to the spacer element.

18. The device of claim 14, wherein the gate structure is a metal gate structure having a work function layer that is disposed on a top surface of a spacer element abutting the sidewall of the gate structure, wherein a top surface of the metal gate structure is coplanar with a top surface of the spacer element.

19. The device of claim 14, wherein the gate structure is a metal gate structure having a work function layer that has at least one sidewall that includes a length that is oblique to a top surface of the semiconductor substrate.

20. The device of claim 14, wherein the gate structure is a metal gate structure having a fill metal layer on a work function layer, wherein the fill metal layer has sidewalls that are perpendicular to a top surface of the semiconductor substrate from a first termination point to a second termination point.