HTO offset for long leffective, better device performance

• US 9,455,352 B2
• Filed: 12/17/2013
• Issued: 09/27/2016
• Est. Priority Date: 12/22/2008
• Status: Active Grant

• Current Assignee: Infineon Technologies Batam PT (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Kinoshita, Hiro, Hui, Angela, Cheng, Ning, Wu, Huaqiang, Choi, Jihwan
• Primary Examiner(s): Dickey, Thomas L
• Application Number:
  US14/109,157
• Publication Number:
  US 20140167138A1
• Time in Patent Office: 1,015 Days
• Field of Search: 257/324, 257/390, 257/E21.679, 257/E27.081, 257/E27.103, 438/257, 438/261, 438/300, 438/301
• US Class Current: 1/1
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.

Claims

1. A dual-bit memory cell comprising:

a charge trapping dielectric stack disposed overlying an essentially planar upper surface of a semiconductor substrate;

a poly gate disposed overlying the charge trapping dielectric stack;

p-type pocket implant regions having a first portion under a peripheral portion of the charge trapping dielectric stack and a second portion adjacent to the charge trapping dielectric stack and disposed in a bit line opening;

spacers laterally adjacent the charge trapping dielectric stack and poly gate, wherein a first portion of each spacer overlies the second portion of each pocket implant region;

a bit line implant region disposed in the semiconductor substrate adjacent the charge trapping dielectric stack and under the bit line opening wherein the bit line implant region has an upper surface congruent with the upper surface of the semiconductor surface; and

a word line.

2. The dual-bit memory cell of claim 1, further comprising a bit line dielectric disposed over the bit line implant region.

3. The dual-bit memory cell of claim 1, wherein the charge trapping dielectric stack comprises two spatially separated charge storage nodes.

4. The dual-bit memory cell of claim 3, wherein the two spatially separated charge storage nodes are physically separated by a central dielectric disposed therebetween.

5. The dual-bit memory cell of claim 1, wherein the word line is disposed overlying the charge trapping dielectric stack.

6. The dual-bit memory cell of claim 1, wherein the charge trapping dielectric stack comprises at least one of silicon nitride, silicon oxynitride, silicon rich nitride and silicates, wherein each is characterized by having a dielectric constant higher than that of silicon dioxide (SiO₂).

7. The dual-bit memory cell of claim 5, wherein the charge trapping dielectric stack further comprises at least one oxide or nitride of Al, Ta, Hf, La, Zr, Ti, Nb, Cr, V, Y, Ce, and/or Pr.

8. The dual-bit memory cell of claim 1, wherein bit line length (BL_L) is 70% or more and 140% or less of the length of the bit line opening (BLO_L).

9. The dual-bit memory cell of claim 1, wherein the bit lines have a concentration of dopants of 5E17 atoms/cm³ or more and 1E21 atoms/cm³ or less.

10. The dual-bit memory cell of claim 1, wherein the bit lines have a depth of 20 nm or more and 300 nm or less.

11. A method of making dual-bit memory cells, comprising:

forming a charge trapping dielectric stack disposed overlying an essentially planar upper surface of a semiconductor substrate;

forming a poly gate disposed overlying the charge trapping dielectric stack;

forming p-type pocket implant regions in the semiconductor substrate, wherein the p-type pocket implant regions have a first portion under a peripheral portion of the charge trapping dielectric stack, and a second portion adjacent to the charge trapping dielectric stack and disposed in a bit line opening;

forming spacers laterally adjacent the charge trapping dielectric stack and the poly gate wherein a first portion of each spacer overlies the second portion of each pocket implant region;

forming a bit line implant region disposed in the semiconductor substrate adjacent the charge trapping dielectric stack and under the bit line opening wherein the bit line implant region has an upper surface congruent with the upper surface of the semiconductor substrate;

forming a word line overlying the charge trapping dielectric stack.

12. The method of claim 11 further comprising forming a bit line dielectric disposed over the bit line implant region in bit line opening.

13. The method of claim 11 further comprising forming two spatially separated charge storage nodes.

14. The method of claim 13, wherein forming two spatially separated charge storage nodes further comprises forming a central dielectric disposed between said two spatially separated charge storage nodes.

15. The method of claim 11, wherein forming pocket implant regions in the semiconductor substrate comprises implanting a dopant into the semiconductor substrate at an angle relative to an upper surface of the semiconductor substrate between 5 degrees and 40 degrees, inclusive.

16. A memory device, comprising:

an array of dual-bit memory cells, wherein each of the dual-bit memory cells comprises,

a charge trapping dielectric stack disposed overlying an essentially planar upper surface of a semiconductor substrate,

a poly gate disposed overlying the charge trapping dielectric stack,

p-type pocket implant regions having a first portion under a peripheral portion of the charge trapping dielectric stack and a second portion adjacent to the charge trapping dielectric stack and disposed in a bit line opening,

spacers laterally adjacent the charge trapping dielectric stack and poly gate, wherein a first portion of each spacer overlies the second portion of each pocket implant region,

a bit line implant region disposed in the semiconductor substrate adjacent the charge trapping dielectric stack and under the bit line opening wherein the bit line implant region has an upper surface congruent with the upper surface of the semiconductor surface, and

a word line;

wherein the array of dual-bit memory cells is arranged in rows and columns such that,

the charge trapping dielectric stack of each of the dual-bit memory cells includes one of the bit line openings and the bit line implant region disposed laterally adjacent on both sides,

two of the dual-bit memory cells in a same row and adjacent columns are separated by and share a common bit line opening and bit line implant region, and

the dual-bit memory cells in the same row share a common word line.

17. The memory device of claim 16 further comprising a bit line dielectric disposed over each of the bit line openings.

18. The memory device of claim 17, wherein the charge trapping dielectric stack of each of the dual-bit memory cells further comprises two spatially separated charge storage nodes.

19. The memory device of claim 17, wherein the two spatially separated charge storage nodes further comprise a central dielectric disposed therebetween.