Method and apparatus for fast locking of a clock generating circuit
First Claim
1. An integrated circuit having a clock generating circuit with a feedback loop and a variable clock signal generator comprising:
- open feedback loop switch logic responsive to a controlled change in power supply voltage indication signal, and operative to selectively open the feedback loop; and
a dynamic fast lock control signal generator operative to selectively apply a stabilizing control signal to the variable clock signal generator in response to opening the feedback loop.
2 Assignments
0 Petitions
Accused Products
Abstract
In a method and apparatus for using a clock generating circuit to minimize settling time after dynamic power supply voltage ramping, a clock signal may be generated using a clock generating circuit having, among other things, open feedback loop switch logic and a dynamic fast lock control signal generator. Whereupon, when in operation, the open feedback loop switch logic is responsive to a controlled change in power supply voltage condition such that a feedback loop of the clock generating circuit is opened during power supply voltage ramping (e.g., during transitions to or from battery conservation modes). In response to opening the feedback loop, the dynamic fast lock control signal generator selectively applies a stabilizing control signal to a variable clock signal generator (e.g., a voltage controlled oscillator) such that the generated clock signal can quickly lock onto the proper target frequency.
9 Citations
30 Claims
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1. An integrated circuit having a clock generating circuit with a feedback loop and a variable clock signal generator comprising:
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open feedback loop switch logic responsive to a controlled change in power supply voltage indication signal, and operative to selectively open the feedback loop; and a dynamic fast lock control signal generator operative to selectively apply a stabilizing control signal to the variable clock signal generator in response to opening the feedback loop. - View Dependent Claims (2, 3, 4, 5)
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6. An integrated circuit having a clock generating circuit with a feedback loop and a variable clock signal generator comprising:
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open feedback loop switch logic responsive to a controlled change in power supply voltage indication signal, and operative to selectively open the feedback loop; a dynamic fast lock control signal generator operative to selectively apply a stabilizing control signal to the variable clock signal generator in response to opening the feedback loop and is responsive to a completed controlled change in power supply voltage indication signal and operative to selectively remove the stabilizing control signal from the variable clock signal generator; and wherein the open feedback loop switch logic control input is operative to selectively close the feedback loop in response to the controlled change in power supply voltage indication signal. - View Dependent Claims (7, 8)
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9. An integrated circuit having a clock generating circuit with a feedback loop and a variable clock signal generator, the clock generating circuit comprising:
a system phase lock loop having; a phase frequency detector responsive to a reference clock signal and a feedback clock signal, and operative to produce a phase adjust signal; a selectively driven charge pump responsive to the phase adjust signal and a controlled change in power supply voltage indication signal, and operative to selectively open the feedback loop and selectively apply a charged control signal to the variable clock signal generator; wherein the variable clock signal generator is responsive to at least one of the charged control signal, a process corner control signal and a stabilizing control signal, and operative to produce a generated clock signal, wherein the feedback clock signal is based upon the generated clock signal; a process corner control signal generator responsive to a chip reset indication signal and operative to selectively apply the process corner control signal; and a dynamic fast lock control signal generator responsive to the generated clock signal and a completed controlled change in power supply voltage indication signal, and operative to selectively apply the stabilizing control signal to the input of the variable clock signal generator. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. An integrated circuit comprising:
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a process corner control signal generator responsive to a chip reset indication signal and operative to produce a process corner control signal; a system phase lock loop comprising a variable clock signal generator that receives in an input thereof, the process corner control signal and operative to produce a generated clock signal; and process corner logic responsive to the generated clock signal and operative to determine which of a plurality of process corners the integrated circuit is operating in based on the generated clock signal. - View Dependent Claims (17)
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18. A method for generating a clock signal using a clock generating circuit located on an integrated circuit having a feedback loop and a variable clock signal generator, the method comprising:
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selectively opening the feedback loop in response to a controlled change in power supply voltage condition; and selectively applying a stabilizing control signal to the variable clock signal generator in response to opening the feedback loop. - View Dependent Claims (19)
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20. A method for generating a clock signal using a clock generating circuit located on an integrated circuit having a feedback loop and a variable clock signal generator, the method comprising:
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selectively opening the feedback loop in response to a controlled change in power supply voltage condition; selectively applying a stabilizing control signal to the variable clock signal generator in response to opening the feedback loop; selectively removing the stabilizing control signal from the variable clock signal generator in response to an absence of the controlled change in power supply voltage condition; and selectively closing the feedback loop in response to the absence of the controlled change in power supply voltage condition. - View Dependent Claims (21, 22)
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23. A method for generating a clock signal using a clock generating circuit located on an integrated circuit having a feedback loop and a variable clock signal generator, the method comprising:
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using a system phase lock loop (PLL) of the clock generating circuit to determine a process corner of the integrated circuit; receiving a desired power supply voltage; selectively opening a feedback loop in response to a controlled change in power supply voltage indication signal; in response to selectively opening the feedback loop, selectively applying a stabilizing control signal to the variable clock signal generator based on the determined process corner of the integrated circuit and the desired power supply voltage; selectively removing the stabilizing control signal from the variable clock signal generator in response to a completed controlled change in power supply voltage indication signal; and selectively closing the feedback loop in response to the controlled change in power supply voltage indication signal. - View Dependent Claims (24, 25, 26)
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27. A method for determining a process corner of an integrated circuit comprising:
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selectively opening a feedback loop of a system phase lock loop (PLL) in response to a chip reset condition; selectively applying a process corner control signal to an input of a variable clock signal generator of the system PLL in response to a chip reset condition; producing a variable clock signal generator output having a frequency based upon the process corner control signal; comparing the variable clock signal generator output frequency to at least one of a plurality of threshold frequencies; and determining the process corner based on the comparison between the variable clock signal generator output frequency and at least one of the plurality of threshold frequencies. - View Dependent Claims (28, 29)
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30. A method for determining a process corner of an integrated circuit comprising:
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selectively opening a feedback loop of a system phase lock loop (PLL) in response to a chip reset condition; selectively applying a power supply voltage to an input of a variable clock signal generator of the system PLL in response to the chip reset condition; producing a variable clock signal generator output having a frequency based upon a process corner control signal; comparing the variable clock signal generator output frequency to at least one of a plurality of threshold frequencies; and determining the process corner based on the comparison between the variable clock signal generator output frequency and at least one of the plurality of threshold frequencies.
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Specification