Wireless communication apparatus with phase noise mitigation

• US 9,455,847 B1
• Filed: 07/27/2015
• Issued: 09/27/2016
• Est. Priority Date: 07/27/2015
• Status: Expired due to Fees

• Current Assignee: Sanguoon Chung
• Original Assignee: Sanguoon Chung
• Inventors: Chung, Sanguoon
• Primary Examiner(s): Lam, Kenneth
• Application Number:
  US14/809,489
• Time in Patent Office: 428 Days
• US Class Current: 1/1
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 27/0014 Carrier regulation of chaotic carriers H04L27/001; for multicarrier receivers H04L27/2657

Abstract

The present invention is a method and apparatus for mitigating phase noise in data communication systems. The present invention provides effective phase noise mitigation with very low latency by combining the decision feedback equalizer and carrier recovery loop effectively. The phase noise estimate is obtained by calculating the phase difference between the input and output of the decision device (DD) in the decision feedback equalizer (DFE) and then applying a digital phase locked loop (DPLL) on the phase difference. Deriving the phase noise estimate from the phase noise estimation process, phase noise mitigation is obtained by multiplying the phase noise estimate at the input signal of the feedforward filter (FFF) and at the input signal of the DD in DFE. An accurate signal-to-noise ratio (SNR) estimate is also obtained in the process of the filter coefficient update process in the DFE.

Claims

1. A wireless communication apparatus that combines DFE and carrier recovery systems, designed for phase noise estimation and correction, comprising:

an electric circuit, wherein the electric circuit is configured to;

a. obtain a phase noise compensated input signal of the FFF by performing a phase noise correction (or compensation) by multiplying an input signal of a DFE with a negative value of a phase noise estimate which is obtained from carrier recovery DPLL (digital phase locked loop);

b. obtain a phase noise compensated input signal of the DD by performing the phase noise correction (or compensation) by multiplying an output signal of the DFE with the negative value of the phase noise estimate which is obtained from carrier recovery DPLL (digital phase locked loop);

c. generate a DD output by finding one of a M signal constellation points which is closest to the phase noise compensated DD input signal in DD;

d. calculate a DD error signal by subtracting a DD output from the DD input signal;

generating the DFE output by operating the DFE using the phase noise compensated input signal of the FFF- and the DD output as an input of FBF;

calculating a normalized DD input-signal by dividing the DD input signal by an energy of the DD input signal;

calculating a normalized DD error by multiplying a complex conjugate of the DD error signal with the normalized DD input signal;

e. calculate a phase noise sample by taking an imaginary part of the normalized DD error;

obtaining a phase noise estimate by passing the phase noise samples to a low pass filter (LPF) and then to an oscillator in the digital phase locked loop (DPLL);

finally, performing phase noise correction by multiplying a respective input signal of the FFF and an output signal of the DFE with the negative value of the phase noise estimate;

wherein the electric circuit further comprises;

a multiplier operating as a phase noise compensator;

a DD output generator that generates the DD output by finding one of the M signal constellation points which is closest to the phase noise compensated DD input signal in DD;

a DD error signal calculator that calculates the DD error signal by subtracting the DD output from the DD input signal;

a normalized DD input-signal calculator that calculates the normalized DD input signal by dividing the DD input signal by the energy of the DD input signal;

a normalized DD error calculator that calculates the normalized DD error by multiplying the complex conjugate of the DD error signal with the normalized DD input signal;

a phase noise sample calculator that calculates the phase noise sample by taking the imaginary part of the normalized DD error; and

a phase noise corrector that corrects phase noise by multiplying the respective input signal of the FFF and the output signal of the DFE with the negative value of the phase noise estimate.

2. A wireless communication apparatus of claim 1, wherein the electric circuit is configured to obtain the phase noise compensated input signal of the FFF by performing the phase noise correction or compensation by multiplying the input signal of the DFE with the negative value of the phase noise estimate which is obtained from carrier recovery DPLL (digital phase locked loop).

3. A wireless communication apparatus of claim 1, wherein the electric circuit is configured to obtain the phase noise compensated input signal of the DD or the DD input, wherein the phase noise compensated input signal of the DD (or DD input) is obtained by performing the phase noise correction (or compensation) by multiplying the output signal of the DFE with the negative value of the phase noise estimate which is obtained from carrier recovery DPLL (digital phase locked loop).

4. A wireless communication apparatus of claim 3, wherein the electric circuit is configured to obtain a signal energy sample by multiplying a DD output with a complex conjugate of the DD output.

5. A wireless communication apparatus of claim 1, wherein the electric circuit is configured to obtain the DD by finding one of the M signal constellation points which is closest to the phase noise compensated DD input signal in DD and by selecting the constellation point as the DD output.

6. A wireless communication apparatus of claim 1, wherein the electric circuit is configured to obtain the DD error signal by subtracting the DD output from the DD input signal.

7. A wireless communication apparatus of claim 1, wherein the electric circuit is configured to obtain the DFE output by operating the DFE and a filter coefficient update processing, wherein the filter coefficient update process uses the phase noise compensated input signal of the FFF, the DD output signal, the DD error signal, and a step size.

8. A wireless communication apparatus of claim 1, wherein the electric circuit is configured to obtain the normalized DD input signal by diving the DD input signal by the energy of the DD input signal.

9. A wireless communication apparatus of claim 1, wherein the electric circuit is configured to obtain the normalized DD error by multiplying the complex conjugate of the DD error signal with the normalized DD input signal.

10. A wireless communication apparatus of claim 1, wherein the electric circuit is configured to obtain the phase noise sample by taking the imaginary part of the normalized DD error.

11. A wireless communication apparatus of claim 1, wherein the electric circuit is configured to obtain the phase noise estimate by passing the phase noise samples to the low pass filter (LPF) and then to the oscillator in the digital phase locked loop (DPLL).

12. A wireless communication apparatus of claim 1, wherein the electric circuit is configured to obtain phase noise correction (or compensation) by multiplying the respective input signal of the FFF and the output signal of the DFE with the negative value of the phase noise estimate.

13. A wireless communication apparatus of claim 1, wherein the electric circuit is configured to estimate signal to noise ratio (SNR) by:

a. calculating a signal energy sample by multiplying the DD output signal with the complex conjugate of the DD output signal;

b. calculating a signal energy estimate by averaging the signal energy sample using 1-pole IIR (infinite impulse response) filter or low pass filter (LPF);

calculating the DD error signal by subtracting the DD output signal from the DD input signal;

c. calculating a noise energy sample by multiplying the DD error signal with the complex conjugate of the DD error signal;

d. calculating a noise energy estimate by averaging the noise energy sample using 1-pole IIR (infinite impulse response) filter or LPF; and

e. calculating SNR by dividing the signal energy estimate by noise energy estimate.

14. A wireless communication apparatus of claim 13, wherein the electric circuit is configured to obtain the signal energy estimate by averaging the signal energy sample using 1-pole IIR (infinite impulse response) filter or low pass filter (LPF).

15. A wireless communication apparatus of claim 13, wherein the electric circuit is configured to obtain the DD error signal by subtracting a DD output from a noise compensated DD input;

wherein the electric circuit is configured to obtain the phase noise compensated input signal of the DD or the DD input, wherein the phase noise compensated input signal of the DD (or DD input) is obtained by performing the phase noise correction (or compensation) by multiplying the output signal of the DFE with the negative value of the phase noise estimate which is obtained from carrier recovery DPLL (digital phase locked loop);

wherein the electric circuit is configured to obtain the DD by finding one of the M signal constellation points which is closest to the phase noise compensated DD input signal in DD and by selecting the constellation point as the DD output.

16. A wireless communication apparatus of claim 13, wherein the electric circuit is configured to obtain the noise energy sample by multiplying the DD error signal with the complex conjugate of the DD error signal.

17. A wireless communication apparatus of claim 13, wherein the electric circuit is configured to obtain a noise energy estimate by averaging the noise energy sample using 1-pole IIR (infinite impulse response) filter or LPF.

18. A wireless communication apparatus of claim 13, wherein the electric circuit is configured to obtain the signal to noise ratio (SNR) by dividing the signal energy estimate by noise energy estimate.