Multi-level clock signal distribution network and integrated circuit

• US 9,459,651 B2
• Filed: 11/04/2011
• Issued: 10/04/2016
• Est. Priority Date: 11/04/2011
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Moheban, Lior, Elazary, Avi, Nave, Amir, Sivan, Noam
• Primary Examiner(s): Chen, Sibin
• Assistant Examiner(s): RETEBO, METASEBIA T
• Application Number:
  US14/349,690
• Publication Number:
  US 20140247080A1
• Time in Patent Office: 1,796 Days
• Field of Search: 327291-297
• US Class Current: 1/1
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines

Abstract

A multi-level clock signal distribution network comprises a plurality of lower network levels comprising at least a first lower network level and a lowermost network level that is connected to one or more lowermost clock signal driving circuits connectable to receive a clock signal; and a topmost network level arranged to distribute the clock signal to a plurality of clocked circuits, and connected to a plurality of topmost clock signal driving circuits connected to receive the clock signal from the first lower network level. The lowermost network level comprises at least one net and each of the plurality of lower network levels except the lowermost network level comprises a plurality of nets and is connected to a corresponding plurality of lower clock signal driving circuits being connected to receive the clock signal from a subjacent one of the plurality of lower network levels, wherein each of the plurality of nets is driven by all nets of the subjacent one.

Claims

1. A multi-level clock signal distribution network, comprising

a lowermost network level connected to a lowermost clock signal driving circuit to receive a clock signal, wherein the lowermost network level comprises a first net;

a plurality of lower network levels, wherein each lower network level comprises a plurality of nets and is connected to a corresponding plurality of lower clock signal driving circuits to receive the clock signal from a subjacent lower network level of the plurality of lower network levels such that each of the plurality of nets of a particular lower network level is driven by all nets of the subjacent lower network level, and wherein the plurality of lower network levels includes a first lower network level that is subjacent to a second lower network level; and

a topmost network level connected to a plurality of clocked circuits to distribute the clock signal to the plurality of clocked circuits, and connected to a plurality topmost clock signal driving circuits to receive the clock signal from the second lower network level;

wherein the nets of said plurality of nets comprised in each of said of lower network levels except said lowermost network level are arranged in a first direction differing from a second direction of the nets located in said subjacent one of said plurality of lower network levels by a constant forty-five degree angle.

2. The multi-level clock signal distribution network as claimed in claim 1, wherein said topmost network level comprises a plurality of nets connected to form a mesh grid.

3. The multi-level clock signal distribution network as claimed in claim 1, wherein the nets of said plurality of nets comprised in each of said plurality of lower network levels are not directly connected with one another within the same lower network level.

4. The multi-level clock signal distribution network as claimed in claim 1, wherein the nets of said plurality of nets comprised in each of said plurality of lower network levels are arranged in parallel with one another.

5. The multi-level clock signal distribution network as claimed in claim 1, wherein said plurality of lower clock signal driving circuits comprised in each of said plurality of lower network levels except said lowermost network level are located at junctions between the nets comprised in each of said plurality of lower network levels and said subjacent one of said plurality of lower network levels.

6. The multi-level clock signal distribution network as claimed in claim 1, wherein each of said plurality of lower network levels except said lowermost network level comprises at least as many nets as its subjacent one.

7. The multi-level clock signal distribution network as claimed in claim 1, wherein said plurality of lower network levels comprises at least three network levels.

8. The multi-level clock signal distribution network as claimed in claim 1, wherein one or more of said plurality of lower network levels except said lowermost network level comprise their respective plurality of nets connected to form a mesh grid.

9. An integrated circuit, comprising a multi-level clock signal distribution network as claimed in claim 1.

10. The integrated circuit as claimed in claim 9, wherein said integrated circuit is a processing device.