Methods and apparatus for managing and controlling power consumption and heat generation in computer systems

• US 9,459,919 B2
• Filed: 02/24/2014
• Issued: 10/04/2016
• Est. Priority Date: 04/05/2006
• Status: Active Grant

• Current Assignee: Data Device Corporation (Transdigm Group Incorporated)
• Original Assignee: Data Device Corporation (Transdigm Group Incorporated)
• Inventors: Conrad, Mark Steven, Hillman, Robert A.
• Primary Examiner(s): Tang, Kenneth
• Application Number:
  US14/188,583
• Publication Number:
  US 20140173610A1
• Time in Patent Office: 953 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 9/4893 taking into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods and systems of operating a computer system including a processor are disclosed. In one aspect, a method includes providing a discretized operating system for controlling applications executed by the computer system, and replacing an idle task of the discretized operating system with a substitute idle task that causes the processor to enter a dormant mode, a priority level of the substitute idle task being the same as a priority level of the idle task.

Claims

1. A method of operating a computer system comprising a processor, the method comprising:

providing a discretized operating system for controlling applications executed by the computer system; and

replacing an idle task of the discretized operating system with a substitute idle task that causes the processor to enter a dormant mode, a priority level of the substitute idle task being the same as a priority level of the idle task.

2. The method of claim 1, wherein the dormant mode is a low latency period dormant mode that requires fewer than fifty processor clock cycles to awaken the processor.

3. The method of claim 1, further comprising:

receiving a first non-operating system interrupt during the dormant mode caused by the substitute idle task; and

servicing the first non-operating system interrupt during a time slice in which the first non-operating system interrupt is received.

4. The method of claim 3, further comprising:

receiving a second non-operating system interrupt during the dormant mode caused by the substitute idle task executed in response to completion of servicing the first non-operating system interrupt; and

servicing the second non-operating system interrupt during the time slice in which the second non-operating system interrupt is received.

21. The method of claim 1, further comprising:

receiving a non-operating system interrupt during the dormant mode caused by the substitute idle task;

servicing the first non-operating system interrupt during a time-slice in which the non-operating system interrupt is received; and

executing the substitute idle task in response to completion of servicing the non-operating system interrupt during the time slice in which the non-operating system interrupt is received.

22. The method of claim 1, wherein the processor remains capable of responding to non-operating system interrupt during the dormant state caused by the substitute idle task.

5. A computer system comprising:

at least one processor; and

a memory storing program code, the memory being coupled to the at least one processor to allow the at least one processor to read the program code, wherein the program code, when executed by the at least one processor, configures the at least one processor to;

provide a discretized operating system for controlling applications executed by the computer system, and

replace an idle task of the discretized operating system with a substitute idle task that causes a particular processor of the one or more processors to enter a dormant mode, a priority level of the substitute idle task being the same as a priority level of the idle task.

6. The computer system of claim 5, wherein the dormant mode is a nap state that disables bus snooping.

7. The computer system of claim 5, wherein the dormant mode is a low latency period dormant mode that requires fewer than fifty processor clock cycles to awaken the particular processor.

8. The computer system of claim 5, wherein the dormant mode is a low latency period dormant mode that requires no more than ten processor clock cycles to awaken the particular processor.

9. The computer system of claim 5, wherein the program code, when executed by the at least one processor, further configures the at least one processor to:

receive a first non-operating system interrupt during the dormant mode caused by the substitute idle task; and

service the first non-operating system interrupt during the time slice in which the first non-operating system interrupt is received.

10. The computer system of claim 9, wherein the first non-operating system interrupt is generated by a stimulus event external to the computer system of the processor.

11. The computer system of claim 9, wherein the first non-operating system interrupt is generated by an event internal to the computer system of the processor.

12. The computer system of claim 9, wherein the program code, when executed by the at least one processor, further configures the at least one processor:

receive a second non-operating system interrupt during the dormant mode caused by the substitute idle task executed in response to completion of servicing the first non-operating system interrupt; and

service the second non-operating system interrupt during the time slice in which the second non-operating system interrupt is received.

13. A method of operating a computer system comprising a processor, the method comprising:

providing a discretized operating system for controlling applications executed by the computer system; and

replacing an idle task of the discretized operating system with a high priority power limiting task that causes the processor to enter a dormant mode.

14. The method of claim 13, further comprising:

receiving an interrupt while the processor is in the dormant mode;

comparing a priority of the interrupt to the priority of the power limiting task; and

servicing the interrupt based on the comparison.

15. The method of claim 13, wherein the power limiting task consumes a predetermined percentage or portion of processing time of the processor during a time slice.

16. The method of claim 13, wherein the power limiting task has the highest priority of any tasks controlled by the operating system.

17. A computer system comprising:

at least one processor; and

a memory storing program code, the memory being coupled to the at least one processor to allow the at least one processor to read the program code, wherein the program code, when executed by the at least one processor, configures the at least one processor to;

provide a discretized operating system for controlling applications executed by the computer system, and

replace an idle task of the discretized operating system with a high priority power limiting task that causes the processor to enter a dormant mode.

18. The computer system of claim 17, wherein the program code, when executed by the at least one processor, further configures the at least one processor to:

receive an interrupt while the processor is in the dormant mode,

compare a priority of the interrupt to the priority of the power limiting task, and

service the interrupt based on the comparison.

19. The computer system of claim 17, wherein the power limiting task is configured to consume a predetermined percentage or portion of processing time of the processor during a time slice.

20. The computer system of claim 17, wherein the power limiting task is configured to have the highest priority of any tasks controlled by the operating system.