Multi-core microprocessor internal bypass bus

• US 9,460,038 B2
• Filed: 11/17/2011
• Issued: 10/04/2016
• Est. Priority Date: 12/22/2010
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Gaskins, Darius D.
• Primary Examiner(s): Dang, Khanh
• Application Number:
  US13/299,014
• Publication Number:
  US 20120239847A1
• Time in Patent Office: 1,783 Days
• Field of Search: 710/105, 710/305, 710/316, 709/213, 709/216, 712/28
• US Class Current: 1/1
• CPC Class Codes: G06F 13/14 Handling requests for interconnection or transfer
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 15/76 Architectures of general purpose stored program computers with program plugboard G06F15/08; multicomputers G06F15/16

Abstract

Microprocessors with multi-core dies that include bypass buses are provided. Each microprocessor comprises a plurality of physical pins for coupling the microprocessor to a processor bus coupled to a chipset. The multi-core die has at least two complementary sets of one or more processing cores, each providing a bus interface coupling respective core inputs and outputs to corresponding processor bus lines. A bypass bus on the die enables cores of the complementary sets to bypass the processor bus and communicate directly with each other. The bypass bus does not carry signals off the die, drive signals on the processor bus to the chipset, or receive chipset-drive signals from the processor bus. Moreover, the microprocessor is operable to detect whether the chipset or a complementary core is driving the processor bus, and if the latter, to select the higher quality bypass bus signals over the corresponding processor bus signals.

Claims

1. A microprocessor, comprising:

a plurality of physical pins for coupling the microprocessor to a bidirectional processor bus coupled to a chipset, the processor bus comprising data and address lines;

a die having a plurality of processing cores, each core having a bus interface coupling respective inputs and outputs of the core to corresponding bidirectional lines of the processor bus; and

a bypass bus on the die that enables at least first and second complementary cores of the die to bypass the processor bus in order to communicate directly with each other, the bypass bus providing bus lines corresponding to all of the data and address lines of the processor bus;

wherein the bypass bus does not carry signals off the die, drive signals on the processor bus to the chipset, or receive chipset-driven signals from the processor bus;

wherein when the first core drives values on the processor bus to the chipset, the bus interface of the second core causes the second core to observe the values driven by the first core directly from the bypass bus rather than from the processor bus; and

wherein when the second core drives values on the processor bus to the chipset, the bus interface of the first core causes the first core to observe the values driven by the second core directly from the bypass bus rather than from the processor bus.

2. The microprocessor of claim 1, wherein the bypass bus comprises wire nets disposed on the die and configured to convey a plurality of output signals from the first core to corresponding inputs of the second core, and a plurality of output signals from the second core to corresponding inputs of the first core.

3. The microprocessor of claim 2, wherein for each processor bus line of a plurality of processor bus lines to which the first and second cores are coupled, corresponding bus bypass lines are provided to connect the first and second cores together.

4. The microprocessor of claim 3, wherein for each processor bus line of the plurality of processor bus lines coupled to the first and second cores, a corresponding first unidirectional bypass bus line is provided going from the first core to the second core, and a corresponding second unidirectional bypass line is provided going from the second core to the first core.

5. The microprocessor of claim 1, wherein each bypass bus line has input and output ends coupled to corresponding bus interface logic of the first and second cores.

6. The microprocessor of claim 5, wherein, for each processor bus line of a plurality of processor bus lines coupled to the first and second cores, the core provides bus interface logic that receives, as a respective input, an output of a bus line interface multiplexer that receives, among the multiplexer'"'"'s selectable inputs, the processor bus line and an output end of a corresponding bypass bus line from the complementary core.

7. The microprocessor of claim 6, wherein the bus line interface multiplexer receives a control input corresponding to whether the chipset, or a complementary core, is driving the processor bus.

8. The microprocessor of claim 7, wherein the core providing the bus line interface multiplexer is:

operable to detect, through analysis of signals on the processor bus, whether the chipset, or a complementary core, is driving the processor bus; and

configured to provide a corresponding control input to its bus line interface multiplexers.

9. The microprocessor of claim 6, wherein, for each processor bus line of a plurality of processor bus lines coupled to the first and second cores, the bus interface logic also comprises a bus line interface transistor for driving a core signal onto a processor bus line, wherein an input end of a corresponding bypass bus line is coupled directly to a core-driven output signal line gating the bus line interface transistor.

10. The microprocessor of claim 5, wherein each bypass bus line has input and output ends and is connected, on its input end, to the gate of a corresponding bus line interface transistor of one of the first and second cores, and on its output end, to an input of a corresponding bus line interface multiplexer of the other of the first and second cores.

11. A microprocessor, comprising:

a die having at least two cores and at least two sets of physical input/output landing pads, pairs of corresponding ones of said sets of landing pads coupling the microprocessor to a bidirectional processor bus coupled to a chipset, the processor bus comprising data and address lines;

bus interfaces coupling respective inputs and outputs of each core to corresponding physical input/output landing pads of the die; and

aa bypass bus on the die that enables at least first and second complementary sets of die cores to bypass the processor bus in order to communicate directly with each other, the bypass bus providing bus lines corresponding to all of the data and address lines of the processor bus;

wherein the bypass bus does not carry signals off the die, drive signals on the processor bus to the chipset, or receive chipset-driven signals from the processor bus;

wherein when the first set of die cores drives values on the processor bus to the chipset, the bus interfaces cause the second set of die cores to observe the values driven by the first set of die cores directly from the bypass bus rather than from the processor bus; and

wherein when the second set of die cores drives values on the processor bus to the chipset, the bus interfaces cause the first set of die cores to observe the values driven by the second set of die cores directly from the bypass bus rather than from the processor bus.

12. The microprocessor of claim 11, wherein each of the first and second complementary sets of die cores comprise a pair of twin cores that share a corresponding set of physical input/output landing pads of the die.

13. The microprocessor of claim 12, wherein for each processor bus line of a plurality of processor bus lines to which the first and second complementary sets of cores are coupled, corresponding bus bypass lines are provided to connect the first and second complementary sets of cores together.

14. The microprocessor of claim 13, wherein for each processor bus line of the plurality of processor bus lines coupled to the complementary sets of first and second cores, a corresponding first unidirectional bypass bus line is provided going from the first complementary set to the second complementary set, and a corresponding second unidirectional bypass line is provided going from the second complementary set to the first complementary set.

15. The microprocessor of claim 11, wherein each bypass bus line has input and output ends coupled to corresponding bus interface logic of the first and second complementary sets of cores.

16. The microprocessor of claim 15, wherein, for each processor bus line of a plurality of processor bus lines coupled to corresponding sets of first and second cores, the cores of the corresponding set provides bus interface logic that receives, as a respective input, an output of a bus line interface multiplexer that receives, among the multiplexer'"'"'s selectable inputs, the processor bus line and an output end of a corresponding bypass bus line from the complementary core.

17. The microprocessor of claim 16, wherein the bus line interface multiplexer receives a control input corresponding to whether the chipset, or a core of a complementary set of cores, is driving the processor bus.

18. The microprocessor of claim 17, wherein one of the cores of the set of cores providing the bus line interface multiplexer is:

operable to detect, through analysis of signals on the processor bus, whether the chipset, or a core of a complementary set of cores, is driving the processor bus; and

configured to provide a corresponding control input to its bus line interface multiplexers.

19. The microprocessor of claim 16, wherein, for each processor bus line of a plurality of processor bus lines coupled to the first and second complementary sets of cores, the bus interface logic also comprises a bus line interface transistor for driving a core signal onto a processor bus line, wherein an input end of a corresponding bypass bus line is coupled directly to a core-driven output signal line gating the bus line interface transistor, wherein the core-driven output signal line is a Boolean OR of output signal lines of the cores of corresponding complimentary set of cores.

20. The microprocessor of claim 15, wherein each bypass bus line has input and output ends and is connected, on its input end, to the gate of a corresponding bus line interface transistor of one of the complementary sets of cores, and on its output end, to an input of a corresponding bus line interface multiplexer of the other of complementary sets of cores.

21. A method of inter-core communication among cores of a multi-core die, the method comprising:

receiving, on a bus interface of a core, both signals from a processor bus connecting the multi-core die to a chipset and signals from a corresponding bypass bus connecting the core to a complementary, bypass-bus-connected core of the multi-core die, wherein the bypass bus does not carry signals off the die, drive signals on the processor bus to the chipset, or receive chipset-driven signals from the processor bus, and wherein the processor bus comprises data and address lines and the bypass bus provides bus lines corresponding to all of the data and address lines of the processor bus;

detecting whether the processor bus is being driven by the chipset or the complementary core; and

if the processor bus is being driven by the complementary core, causing the bus interface to select signals from the bypass bus instead of signals from the processor bus to drive corresponding core inputs.

22. A method of inter-core communication among cores of a multi-core die, the method comprising:

receiving, on a bus interface shared by a set of twin cores of the die, both a first set of signals from a processor bus connecting the multi-core die to a chipset and a second set of signals from a corresponding bypass bus connecting the set of twin cores to a complementary, bypass-bus-connected set of twin cores of the multi-core die, wherein the first and second sets of signals represent the same values, wherein the bypass bus does not carry the second set of signals off the die, drive the second set of signals on the processor bus to the chipset, or receive chipset-driven signals from the processor bus, and wherein the processor bus comprises data and address lines and the bypass bus provides bus lines corresponding to all of the data and address lines of the processor bus;

detecting whether the processor bus is being driven by the chipset or a core of the complementary set of twin cores; and

if the processor bus is being driven by a core of the complementary set of twin cores, causing the bus interface to select the second set of signals from the bypass bus instead of the first set of signals from the processor bus to drive corresponding core inputs.