Static random access memory with bitline boost
First Claim
1. A static random access memory comprising:
- a memory cell array comprising a plurality of memory cells;
a control logic configured to generate a first write clock signal and a second write clock signal in response to a received clock signal, wherein each of the first and second write clock signals has a single pulse width during a cycle of the clock signal, the single pulse width being shorter than a pulse width of the clock signal;
a row decoder connected to the plurality of memory cells through a plurality of word lines and configured to select a word line in response to the second write clock signal during a write operation;
a column selector connected to the plurality of memory cells through a plurality of bit lines and a plurality of inverted bit lines and configured to select a bit line and an inverted bit line;
a sense amplifier connected to the bit line and the inverted bit line selected by the column selector and configured to sense states of the selected bit line and the selected inverted bit line during a read operation; and
a write driver connected to the bit line and the inverted bit line selected by the column selector and configured to bias the selected bit line and the selected inverted bit line in response to the first write clock signal during the write operation.
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Accused Products
Abstract
A static random access memory includes a memory cell array, a control logic configured to generate a first write clock signal and a second write clock signal each of which having a pulse width shorter than a pulse width of a clock signal in response to the clock signal, a row decoder configured to select a word line in response to the second write clock signal during a write operation, a column selector configured to select a bit line and an inverted bit line, a sense amplifier configured to sense states of the selected bit line and the selected inverted bit line during a read operation and a write driver configured to bias the selected bit line and the selected inverted bit line in response to the first write clock signal during the write operation.
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Citations
18 Claims
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1. A static random access memory comprising:
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a memory cell array comprising a plurality of memory cells; a control logic configured to generate a first write clock signal and a second write clock signal in response to a received clock signal, wherein each of the first and second write clock signals has a single pulse width during a cycle of the clock signal, the single pulse width being shorter than a pulse width of the clock signal; a row decoder connected to the plurality of memory cells through a plurality of word lines and configured to select a word line in response to the second write clock signal during a write operation; a column selector connected to the plurality of memory cells through a plurality of bit lines and a plurality of inverted bit lines and configured to select a bit line and an inverted bit line; a sense amplifier connected to the bit line and the inverted bit line selected by the column selector and configured to sense states of the selected bit line and the selected inverted bit line during a read operation; and a write driver connected to the bit line and the inverted bit line selected by the column selector and configured to bias the selected bit line and the selected inverted bit line in response to the first write clock signal during the write operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A static random access memory comprising:
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a memory cell array including a plurality of memory cells; a row decoder connected to the plurality of memory cells through a plurality of word lines and configured to select a word line during a write operation; a column selector connected to the plurality of memory cells through a plurality of bit lines and a plurality of inverted bit lines and configured to select a bit line and an inverted bit line; a sense amplifier connected to the bit line and the inverted bit line selected by the column selector and configured to sense states of the selected bit line and the selected inverted bit line during a read operation; a write driver connected to the bit line and the inverted bit line selected by the column selector and configured to boost one of the selected bit line and the selected inverted bit line to a negative voltage during the write operation; and a control logic configured to control the row decoder and the write driver in response to a clock signal externally provided, wherein the control logic controls the row decoder to apply a turn-on voltage to the selected word line in response to a first edge of the clock signal, and wherein an entire duration of a write cycle, in which the write operation is performed in response to the clock signal, is shorter than a pulse width of the clock signal. - View Dependent Claims (13, 14)
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15. A method of performing a write operation of a memory device comprising a plurality of memory cells, the method comprising:
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selecting a word line from among a plurality of word lines associated with the plurality of memory cells; applying a turn-on voltage to the selected word line in response to a clock signal; selectively discharging one of a bit line or an inverted bit line in response to write data and the clock signal during a predetermined write time; and boosting one of the discharged bit line or inverted bit line to a negative voltage in response to an elapse of the predetermined write time, wherein an entire duration of a write cycle, in which the write operation is performed in response to the clock signal, is shorter than a pulse width of the clock signal. - View Dependent Claims (16, 17, 18)
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Specification