Semiconductor memory having both volatile and non-volatile functionality and method of operating

• US 9,460,790 B2
• Filed: 08/28/2015
• Issued: 10/04/2016
• Est. Priority Date: 10/24/2007
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Primary Examiner(s): Byrne, Harry W
• Assistant Examiner(s): REIDLINGER, RONALD LANCE
• Application Number:
  US14/839,682
• Publication Number:
  US 20150371707A1
• Time in Patent Office: 403 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/225 Preventing erasure, programming or reading when power supply voltages are outside the required ranges
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H01L 29/7887 : Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H01L 29/792 : with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7923 : Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 12/00 : Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/056 : the transistor being a FinFET
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/36 : the transistor being a FinFET
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/42 : Simultaneous manufacture of periphery and memory cells
• CPC Class Codes: H10B 43/30 : characterised by the memory core region
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region

Abstract

Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

Claims

1. A method of operating a semiconductor memory cell having a fin structure, said method comprising:

providing the memory cell to have a floating body for storing data as volatile memory and a floating gate or trapping layer for storing data as non-volatile memory;

and transferring a state of said non-volatile memory to said volatile memory based on said state of said non-volatile memory state when power is restored to the memory cell,

wherein said transferring said non-volatile memory state to said volatile memory is a non-algorithmic process.

2. The method of claim 1, wherein said volatile memory is configured to a predetermined state prior to being charged based on charge stored in said non-volatile memory.

3. The method of claim 1, further comprising configuring said non-volatile memory to a predetermined state after said transferring said non-volatile memory state to said volatile memory.

4. The method of claim 1, wherein said non-algorithmic process is parallel.

5. The method of claim 1, wherein data stored in said volatile memory as a result of said transferring comprises a charge that is complementary to a charge of said non-volatile memory.

6. A method of operating a semiconductor memory cell having a fin structure comprising:

a floating body region configured to be charged to a level indicative of a state of the memory cell to store the state as volatile memory; and

a floating gate or trapping layer insulated from said floating body region;

the method comprising;

restoring power to said memory cell; and

charging said floating body region based on charge stored in said floating gate or trapping layer upon restoration of power to said memory cell,

wherein said charging said floating body region based on charge stored in said floating gate or trapping layer is a non-algorithmic process.

7. The method of claim 6, wherein said floating body region is configured to a predetermined state prior to being charged based on charge stored in said floating gate or trapping layer.

8. The method of claim 6, further comprising configuring said floating gate or trapping layer to a predetermined state after said floating body region is charged to a level based on charge stored in said floating gate or trapping layer.

9. The method of claim 6, wherein said memory cell functions as a volatile memory upon said restoration of power to said memory cell.

10. The method of claim 6, wherein said non-algorithmic process is parallel.

11. The method of claim 6, wherein said floating body is charged with a charge complementary to said charge stored in said floating gate or trapping layer.

12. A method of operating a semiconductor memory cell having a fin structure comprising:

a floating body region configured to be charged to a level indicative of a state of the memory cell to store the state as volatile memory; and

a floating gate or trapping layer insulated from said floating body region;

the method comprising transferring said volatile memory state to the floating gate or trapping layer when power to the cell is interrupted;

wherein electron injection into said floating gate or trapping layer occurs when said volatile memory is in a first state, and

wherein no electron injection into said floating gate or trapping layer occurs when said memory cell is in a second state,

wherein said transferring is a non-algorithmic process.

13. The method of claim 12, wherein said charge stored in said floating body region is positive in said first state.

14. The method of claim 12, wherein said charge stored in said floating body region is neutral in said second state.

15. The method of claim 12, wherein said charge stored in said floating body region is less positive in said second state relative to said charge stored in said floating body region in said first state.

16. The method of claim 12, wherein said non-algorithmic process is parallel.