Data clock synchronization in hybrid memory modules

• US 9,460,791 B1
• Filed: 12/08/2015
• Issued: 10/04/2016
• Est. Priority Date: 12/08/2015
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Inphi Corporation
• Inventors: Shallal, Aws, Giddens, Larry Grant
• Primary Examiner(s): Pham, Ly D
• Application Number:
  US14/963,082
• Time in Patent Office: 301 Days
• Field of Search: 365/194, 365/189.05, 365/233.1
• US Class Current: 1/1
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/08 Control thereof
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1093 Input synchronization
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

Disclosed herein are techniques for implementing data clock synchronization in hybrid memory modules. Embodiments comprise a clock synchronization engine at a command buffer to generate a synchronized data clock having a phase relationship with data signals from a non-volatile memory controller that compensates for various synchronous and/or asynchronous delays to facilitate latching of the data signals at certain DRAM devices (e.g., during data restore operations). Other embodiments comprise a divider to determine the frequency of the synchronized data clock by dividing a local clock signal from the non-volatile memory controller by a selected divider value. Some embodiments comprise a set of synchronization logic that invokes the generation of the synchronized data clock signal responsive to receiving a certain local command and/or frame pulse from the non-volatile memory controller. In other embodiments, certain fixed and/or programmable delay elements can be implemented to compensate for various asynchronous delays.

Claims

1. A memory system comprising:

one or more DRAM devices;

at least one non-volatile memory controller coupled to the DRAM devices to send one or more data signals to the DRAM devices;

at least one command buffer coupled to the non-volatile memory controller and the DRAM devices, to receive a local clock signal from the non-volatile memory controller, and to provide at least one synchronized data clock signal to the DRAM devices; and

a clock synchronization engine at the command buffer to generate the synchronized data clock signal based at least in part on the local clock signal, wherein a first phase relationship between the synchronized data clock signal and the data signals facilitate latching of the data signals at the DRAM devices, and wherein the first phase relationship compensates for at least one of, one or more synchronous delays, or one or more asynchronous delays.

2. The memory system of claim 1, further comprising a divider to determine a data clock signal frequency corresponding to the synchronized data clock signal based at least in part on a local clock signal frequency corresponding to the local clock signal.

3. The memory system of claim 2, wherein the data clock signal frequency is related to the local clock signal frequency by a divider value.

4. The memory system of claim 3, wherein the divider value is selectable from a plurality of available divider values.

5. The memory system of claim 4, wherein the available divider values comprise at least one of, 4, 2, or 1.

6. The memory system of claim 1, further comprising a set of synchronization logic to issue an alignment pulse to trigger the clock synchronization engine to generate the synchronized data clock signal.

7. The memory system of claim 6, wherein the alignment pulse is issued responsive to a local command received at the command buffer.

8. The memory system of claim 6, wherein the synchronized data clock signal is enabled a second quantity of local clock cycles associated with the local clock signal following the alignment pulse.

9. The memory system of claim 6, wherein the alignment pulse is issued a first quantity of local clock cycles associated with the local clock signal following a frame pulse received at the command buffer from the non-volatile memory controller.

10. The memory system of claim 9, wherein the first quantity of local clock cycles is based at least in part on the synchronous delays.

11. The memory system of claim 1, further comprising a delay controller to select one or more programmable delay elements.

12. The memory system of claim 11, wherein the programmable delay elements are selected based at least in part the asynchronous delays.

13. The memory system of claim 1, further comprising a delay compensator to generate a phase delay characterizing a second phase relationship between the local clock signal and the data signals.

14. The memory system of claim 13, wherein the phase delay is determined based at least in part on the asynchronous delays.

15. The memory system of claim 13, wherein the phase delay is generated by selecting one or more programmable delay elements.

16. The memory system of claim 1, further comprising one or more flash memory devices.

17. The memory system of claim 16, wherein the data signals represent a set of data stored on the flash memory devices.

18. The memory system of claim 1, wherein the data signals are latched at the DRAM devices in at least one burst.

19. The memory system of claim 1, wherein the synchronous delays comprise at least one of, a deterministic delay, a logic stage delay, or a flip-flop delay.

20. The memory system of claim 1, wherein the asynchronous delays comprise at least one of, a propagation delay, a gate delay, a buffer delay, or a printed circuit board trace delay.