AC stress mode to screen out word line to word line shorts

• US 9,460,809 B2
• Filed: 07/10/2014
• Issued: 10/04/2016
• Est. Priority Date: 07/10/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Magia, Sagar, Sabde, Jagdish
• Primary Examiner(s): Merant, Guerrier
• Application Number:
  US14/328,021
• Publication Number:
  US 20160012913A1
• Time in Patent Office: 817 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/27 Built-in tests
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2029/1202 Word line control
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair

Abstract

A number of techniques for determining defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Word line to word shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used determine word line to word line leaks between different blocks. Select gate leak line leakage, both the word lines and other select lines, is consider, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques for determining shorts between bit lines and low voltage circuitry, as in the sense amplifiers, are presented.

Claims

1. A method of determining whether word lines are defective, the method comprising:

performing an intra-block stress operation on a selected block of non-volatile memory cells formed along word lines in a memory circuit, the stress operation having a plurality of stress cycles where each stress cycle for the selected block includes;

applying a high voltage level to a first set of one or more word lines of the selected block while concurrently setting a second set of one or more word lines of the selected block at a low voltage level, where at least one word line of the first set is adjacent to at least one word line of the second set; and

subsequently applying the high voltage level to the second set of word lines while concurrently setting the first set of word lines at the low voltage level; and

subsequent to performing the plurality of stress cycles on the selected block, performing a defect determination operation, including;

performing a write operation on the selected block; and

determining whether the write operation was successful.

2. The method of claim 1, wherein the first and second sets of word lines are respectively even and odd word lines of the selected block.

3. The method of claim 1, wherein determining whether the write operation was successful comprises determining that the number of cells along a word line that fail to verify exceeds a predetermined limit.

4. The method of claim 1, wherein determining whether the operation was successful comprises determining that the write operation failed based on the number of programming loops exceeding a limit.

5. The method of claim 1, further comprising:

in response to determining that the write operation was not successful, marking the block as defective.

6. The method of claim 1, wherein the defect determination operation further includes:

subsequently performing a read operation on the selected block; and

determining whether the data read from the selected block is corrupted.

7. The method of claim 6, wherein determining whether the data read from the selected blocks is corrupted includes comparing the data as read with the data as programmed.

8. The method of claim 7, wherein the data as programmed is a predetermined pattern of known random data.

9. The method of claim 7, wherein determining whether the data read from the selected block is corrupted includes determining that the number of incorrect bits in the data as read exceeds a predetermined limit.

10. The method of claim 6, wherein determining whether the data read from the selected blocks is corrupted is based on an ECC result.

11. The method of claim 6, further comprising:

in response to determining that the data read from the selected block is corrupted, marking the block as defective.

12. The method of claim 1, wherein the array is formed according to a NAND type architecture.

13. The method of claim 1, wherein the memory circuit is a monolithic three-dimensional semiconductor memory device where the memory cells are arranged in multiple physical levels above a silicon substrate and comprise a charge storage medium.

14. The method of claim 13, wherein the plurality of blocks arc formed of a plurality of NAND strings, each having multiple memory cells connected in series between one or more source select gates and one or more drain select gates, the memory cells being connected along word lines and the source and drain select gates being respectively connected along source and drain select lines, the NAND strings being formed above a P well and each connected, though the corresponding drain select gates, to an associated bit line, and

wherein the NAND strings run in a vertical direction relative to the substrate, and the word lines, and source and drain select lines, and bit lines run in a horizontal direction relative to the substrate.

15. The method of claim 1, wherein the intra-block stress operation and subsequent defect determination operations are performed as a built in self-test process.

16. The method of claim 1, wherein the high voltage level is within the range of programming voltage used during write operation.

17. The method of claim 1, wherein the low voltage level is ground.

18. The method of claim 1, wherein the number of stress cycles is a settable parameter.

19. The method of claim 1, wherein the duration of applying the high voltage level is a settable parameter.

20. The method of claim 1, wherein the duration of applying the low voltage level is a settable parameter.

21. The method of claim 1, wherein the rise and fall times for applying the high voltage level are settable parameters.

22. The method of claim 1, wherein the rise and fall times for applying the low voltage level are settable parameters.

23. The method of operating claim 1, Therein the stress operation further includes:

concurrently with applying a high voltage level to the first set of word lines while concurrently setting a second set word lines at a low voltage level, setting a first select gate line adjacent to a word line of the first set at the low voltage; and

concurrently with applying the high voltage level to the second set of word lines while concurrently setting the first set of word lines at the low voltage level, applying the high voltage level to the first select gate line.

24. A system for determining whether word lines are defective, the system comprising:

a memory array comprising blocks of non-volatile memory cells formed along word lines;

sensing circuitry coupled to the memory array, the sensing circuitry configured to;

perform an intra-block stress operation on a selected block of the non-volatile memory cells, the stress operation having a plurality of stress cycles where each stress cycle for the selected block includes;

applying a high voltage level to a first set of one or more word lines of the selected block while concurrently setting a second set of one or more word lines of the selected block at a low voltage level, where at least one word line of the first set is adjacent to at least one word line of the second set; and

subsequently applying the high voltage level to the second set of word lines while concurrently setting the first set of word lines at the low voltage level; and

subsequent to performing the plurality of stress cycles on the selected block, perform a defect determination operation, including;

performing a write operation on the selected block; and

determining whether the write operation was successful.

25. The system of claim 24, wherein the sensing circuitry is further configured to apply the high voltage level and low voltage level to even and odd word lines of the selected block as the first and second sets of word lines, respectively.

26. The system of claim 24, wherein the sensing circuitry is further configured such that the determining whether the write operation was successful comprises determining that the number of cells along a word line that fail to verify exceeds a predetermined limit.

27. The system of claim 24, wherein the sensing circuitry is further configured such that the determining whether the write operation was successful comprises determining that the write operation failed based on the number of programming loops exceeding a limit.

28. The system of claim 24, wherein the sensing circuitry is further configured such that the defect determination operation further includes:

subsequent to determining whether the write operation was successful, performing a read operation on the selected block; and

determining whether the data read from the selected block is corrupted.

29. The system of claim 28, wherein the sensing circuitry is further configured such that determining whether the data read from the selected blocks is corrupted includes comparing the data as read with the data as programmed.

30. The system of claim 29, wherein the sensing circuitry is further configured such that the data as programmed is a predetermined pattern of known random data.

31. The system of claim 29, wherein the sensing circuitry is further configured such that the determining whether the data read from the selected block is corrupted includes determining that the number of incorrect bits in the data as read exceeds a predetermined limit.

32. The system of claim 28, wherein the sensing circuitry is further configured such that the determining whether the data read from the selected blocks is corrupted is based on an ECC result.

33. The system of claim 24, wherein the memory array has a NAND type architecture.

34. The system of claim 24, further comprising a monolithic three-dimensional semiconductor memory device where the memory cells are arranged in multiple physical levels above a silicon substrate and comprise a charge storage medium.

35. The system of claim 34, herein blocks of the memory array are formed of a plurality of NAND strings, each having multiple memory cells connected in series between one or more source select gates and one or more drain select gates, the memory cells being connected along word lines and the source and drain select gates being respectively connected along source and drain select lines, the NAND strings being formed above a P well and each connected, though the corresponding drain select gates, to an associated bit line, and

wherein the NAND strings run in a vertical direction relative to the substrate, and the word lines, and source and drain select lines, and bit lines run in a horizontal direction relative to the substrate.

36. The system of claim 24, wherein the sensing circuitry is further configured such that the high voltage level is within the range of programming voltage used during write operation.

37. The system of claim 24, wherein the sensing circuitry is further configured such that the number of stress cycles is a settable parameter.

38. The system of claim 24, wherein the sensing circuitry is further configured such that the duration of applying the high voltage level is a settable parameter and the duration of applying the low voltage level are settable parameters.

39. The system of claim 24, wherein the sensing circuitry is further configured such that the rise arid fall times for applying the high voltage level are settable parameters and the rise and fall times for applying the low voltage level are settable parameters.

40. The system of operating claim 24, wherein the sensing circuitry is further configured such that the stress operation further includes:

concurrently with applying a high voltage level to the first set of word lines while concurrently setting a second set word lines at a low voltage level, setting a first select gate line adjacent to a word line of the first set at the low voltage; and

concurrently with applying the high voltage level to the second set of word lines while concurrently setting the first set of word lines at the low voltage level, applying the high voltage level to the first select gate line.