Horizontal gate all around device isolation

• US 9,460,920 B1
• Filed: 06/30/2015
• Issued: 10/04/2016
• Est. Priority Date: 05/11/2015
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Sun, Shiyu, Chudzik, Michael, Yoshida, Naomi, Guarini, Theresa Kramer, Jun, Sung Won, Colombeau, Benjamin
• Primary Examiner(s): Picardat, Kevin M
• Application Number:
  US14/755,099
• Time in Patent Office: 462 Days
• Field of Search: 438/437, 438/439, 438/442, 438/452
• US Class Current: 1/1
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Embodiments described herein generally relate to methods and apparatus for horizontal gate all around (hGAA) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. The different materials may be silicon containing materials and one or more III/V materials. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

Claims

1. A method of forming a semiconductor device, comprising:

forming a superlattice structure on a substrate, wherein the superlattice structure comprises;

a first material layer;

a second material layer; and

a third material layer;

patterning the superlattice structure;

etching the superlattice structure and the substrate;

performing a liner deposition process to form a liner on the superlattice structure;

performing a shallow trench isolation process to deposit an oxide material layer on the substrate; and

performing an annealing process to oxidize at least one of the first material layer, the second material layer, or the third material layer to form a buried oxide layer.

2. The method of claim 1, wherein the first material layer and the second material layer are disposed within the superlattice structure in an alternating stacked arrangement.

3. The method of claim 1, wherein the second material layer and the third material layer comprise silicon germanium.

4. The method of claim 3, wherein the second material layer comprises about 70% silicon and about 30% germanium, and the third material layer comprises about 30% silicon and about 70% germanium.

5. The method of claim 4, wherein the second material layer is disposed on the substrate and the third material layer is disposed on the second material layer.

6. The method of claim 1, wherein the substrate and the first material layer comprise a silicon containing material.

7. The method of claim 1, wherein the liner deposition process further comprises:

a thermal oxidation process;

a nitridation process; and

an annealing process.

8. The method of claim 1, wherein the liner comprises an oxynitride material.

9. The method of claim 1, further comprising:

performing a flowable chemical vapor deposition process to deposit the oxide material layer.

10. The method of claim 1, wherein the annealing process comprises performing a steam annealing process at a temperature of between about 300°

C. and about 800°

C.

11. The method of claim 10, further comprising:

performing a dry annealing process after the steam annealing process, the dry annealing process performed at a temperature of between about 500°

C. and about 1000°

C.

12. A method of forming a semiconductor device, comprising:

forming a superlattice structure on a substrate, wherein the superlattice structure comprises;

a silicon material layer;

a low germanium content silicon germanium material layer; and

a high germanium content silicon germanium material layer;

patterning the superlattice structure;

etching the superlattice structure and the substrate;

performing a liner deposition process to form an oxynitride liner on the superlattice structure;

performing a shallow trench isolation process to deposit an oxide material layer on the substrate; and

performing an annealing process to oxidize the high germanium content silicon germanium material layer to form a buried oxide layer.

13. The method of claim 12, wherein the silicon material layer and the low germanium content silicon germanium material layer are disposed within the superlattice structure in an alternating stacked arrangement.

14. The method of claim 12, wherein the low germanium content material layer comprises about 70% silicon and about 30% germanium and the high germanium content material layer comprises about 30% silicon and about 70% germanium.

15. The method of claim 14, wherein the high germanium content silicon germanium material layer is disposed on the substrate.

16. The method of claim 14, wherein the low germanium content silicon germanium material layer is disposed on the substrate and the high germanium content material layer is disposed on the low germanium content material layer.

17. The method of claim 12, wherein the annealing process comprises performing a steam annealing process at a temperature of between about 300°

C. and about 800°

C. and performing a dry annealing process after the steam annealing process at a temperature of between about 500°

C. and about 1000°

C.

18. A method of forming a semiconductor device, comprising:

forming a superlattice structure on a substrate, wherein the superlattice structure comprises;

a silicon material layer;

a first silicon germanium material layer comprising about 30% germanium; and

a second silicon germanium material layer comprising about 70% germanium, wherein the silicon material layer, the first silicon germanium material layer, and the second silicon germanium layer are disposed in a stacked arrangement;

performing a liner deposition process to form an oxynitride liner on the superlattice structure;

performing a shallow trench isolation process to deposit an oxide material layer on the substrate;

performing an annealing process to oxidize the second silicon germanium material layer to form a buried oxide layer; and

performing a shallow trench isolation recess process.

19. The method of claim 18, wherein the annealing process comprises performing a steam annealing process at a temperature of between about 300°

C. and about 800°

C.

20. The method of claim 19, further comprising:

performing a dry annealing process after the steam annealing process at a temperature of between about 500°

C. and about 1000°

C.