Semiconductor device and structure

• US 9,460,978 B1
• Filed: 04/17/2013
• Issued: 10/04/2016
• Est. Priority Date: 12/29/2012
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Cronquist, Brian, Sekar, Deepak
• Primary Examiner(s): Armand, Marc
• Assistant Examiner(s): JEAN BAPTISTE, WILNER
• Application Number:
  US13/864,243
• Time in Patent Office: 1,266 Days
• Field of Search: 257/347, 257/712, 257/758
• US Class Current: 1/1
• CPC Class Codes: H01L 21/4871 Bases, plates or heatsinks
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/373 Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
• CPC Class Codes: H01L 23/3732 Diamonds
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/098 : the components being PN junction gate field-effect transistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A 3D semiconductor device, including: a first layer including first transistors; a second layer overlying the first transistors and including second transistors; wherein the second layer includes a through layer via with a diameter of less than 150 nm; and a Phase-Lock-Loop (PLL) circuit, where the Phase-Lock-Loop (PLL) circuit is connected to at least one input structure, and where the least one input structure is designed to connect an input to the device from external devices.

Claims

1. A 3D semiconductor device, comprising:

a first layer comprising first transistors;

a second layer overlying said first transistors and comprising second transistors;

wherein said second layer comprises a first through layer via with a diameter of less than 150 nm and a second through layer via,

wherein said second through layer via is part of a heat removal structure of said device; and

a Phase-Lock-Loop (PLL) circuit,

wherein said Phase-Lock-Loop (PLL) circuit is connected to at least one input structure, and

wherein said least one input structure is designed to connect an input to said device from external devices.

2. The 3D semiconductor device according to claim 1, further comprising:

a thermal connection path from said second transistors to a top or bottom surface of said device,

wherein said thermal connection path has a thermal conductivity greater than 10 W/m-K.

3. The 3D semiconductor device according to claim 1, further comprising:

a heat-spreader layer disposed between said first layer and said second layer, and

a thermal connection path from said heat-spreader layer to a top or bottom surface of said device.

4. The 3D semiconductor device according to claim 1, further comprising:

a power distribution network to provide power to said second transistors,

wherein said power distribution network provides a heat removal path to at least one of said second transistors.

5. The 3D semiconductor device according to claim 1, further comprising:

at least one thermally conductive and electrically non-conducting contact to at least one of said second transistors.

6. The 3D semiconductor device according to claim 1, further comprising:

a power distribution network to provide power to said second transistors,

wherein said device comprises a heat removal path between said power distribution network and a top or bottom surface of said device.

7. A 3D semiconductor device, comprising:

a first layer comprising first transistors;

a second layer overlying said first transistors and comprising second transistors;

wherein said second layer comprises a first through layer via with a diameter of less than 150 nm and a second through layer via,

wherein said second through layer via is part of a heat removal structure of said device, and

wherein said first layer comprises at least one first circuit comprising said first transistors, said at least one first circuit is circumscribed by a first guard ring, and

wherein said second layer comprises at least one second circuit comprising said second transistors, said at least one second circuit is circumscribed by a second guard ring, and

wherein said second guard ring overlays said first guard ring.

8. The 3D semiconductor device according to claim 7, further comprising:

a thermal connection path from said second transistors to a top or bottom surface of said device,

wherein said thermal connection path has a thermal conductivity greater than 10 W/m-K.

9. The 3D semiconductor device according to claim 7, further comprising:

a heat-spreader layer between said first layer and said second layer, and

a thermal connection path from said heat-spreader layer to a top or bottom surface of said device.

10. The 3D semiconductor device according to claim 7, further comprising:

a power distribution network to provide power to said second transistors,

wherein said power distribution network provides a heat removal path to at least one of said second transistors.

11. The 3D semiconductor device according to claim 7, further comprising:

at least one thermally conductive and electrically non-conducting contact to at least one of said second transistors.

12. The 3D semiconductor device according to claim 7, further comprising:

a power distribution network to provide power to said second transistors,

wherein said device comprises a heat removal path between said power distribution network and a top or bottom surface of said device.

13. A 3D semiconductor device, comprising:

a first layer comprising first transistors;

a second layer overlying said first transistors and comprising second transistors;

wherein said second layer comprises a first through layer via with a diameter of less than 150 nm and a second through layer via,

wherein said second through layer via is part of a heat removal structure of said device; and

an electrically conductive path between at least one of said second transistors and at least one of said first transistors,

wherein said electrically conductive path comprises said first through-silicon-via, and

wherein said second transistors comprise a raised source and drain.

14. The 3D semiconductor device according to claim 13, further comprising:

a thermal connection path from said second transistors to a top or bottom surface of said device,

wherein said thermal connection path has a thermal conductivity greater than 10 W/m-K.

15. The 3D semiconductor device according to claim 13, further comprising:

a heat-spreader layer between said first layer and said second layer,

wherein said heat-spreader layer comprises a thermal conductivity greater than 10 W/m-K.

16. The 3D semiconductor device according to claim 13, further comprising:

a power distribution network to provide power to said second transistors,

wherein said power distribution network provides a heat removal path to at least one of said second transistors.

17. The 3D semiconductor device according to claim 13, further comprising:

at least one thermally conductive and electrically non-conducting contact to at least one of said second transistors.