Bipolar ESD protection device with integrated negative strike diode

• US 9,461,032 B1
• Filed: 11/05/2015
• Issued: 10/04/2016
• Est. Priority Date: 11/05/2015
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Edwards, Henry Litzmann
• Primary Examiner(s): Lebentritt, Michael
• Application Number:
  US14/933,661
• Time in Patent Office: 334 Days
• Field of Search: 257/355
• US Class Current: 1/1
• CPC Class Codes: H01L 27/0259 using bipolar transistors as protective elements
• CPC Class Codes: H01L 29/0626 with a localised breakdown region, e.g. built-in avalanching region in self-protected thyristors H01L29/7424
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/7304 the device being a resistive element, e.g. ballasting resistor transistors integrated with resistors H01L27/075
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/866 Zener diodes

Abstract

A bipolar ESD protection device includes a substrate having a p-type epi layer thereon including an epi region over an n-buried layer (NBL). An n-type isolation tank (iso tank) includes a deep n+ region and NBL for containing an isolated epi region of the epi region. An NPN transistor and an avalanche diode are formed in the isolated epi region. The NPN transistor includes an emitter within a base having a base contact and the collector is a top portion of NBL. The avalanche diode includes a p-type anode region including an anode contact and an n-type cathode region having a cathode contact. The anode region and base are resistively coupled through the epi region. A ground connection couples the emitter to the anode contact and a strike node connection couples the cathode contact to an n+ isolation contact.

Claims

1. A bipolar ESD protection device (ESD device), comprising:

a substrate having a p-type epi layer (p-epi layer) thereon comprising a p-type epi region over an n-buried layer (NBL);

an n-type isolation tank (iso tank) comprising a deep n+ region (deep n+), said NBL containing a p-type isolated epi region of said epi region, and said iso tank having an n+ isolation contact;

an NPN transistor and an avalanche diode both formed in said isolated epi region;

said NPN transistor including an emitter within a base having a base contact and a collector comprising a top portion of said NBL;

said avalanche diode including a p-type anode region including an anode contact and an adjacent n-type cathode region having a cathode contact;

wherein said anode region and said base are resistively coupled together through said isolated epi region;

a ground connection coupling said emitter to said anode contact, and

a strike node connection coupling said cathode contact to said n+ isolation contact.

2. The ESD device of claim 1, wherein said iso tank comprises an outer deep trench isolation ring (DT ring) framing said NPN transistor and said avalanche diode, and wherein said deep n+ is on a sidewall of a dielectric liner of said DT ring under a surface nwell region for connecting to said NBL.

3. The ESD device of claim 1, wherein said deep n+ comprises a vertically-diffused deep n+ region having a lateral diffusion of at least one micron.

4. The ESD device of claim 1, wherein said resistively coupled for said anode region and said base comprises a resistance of 30 ohms to 3,000 ohms.

5. The ESD device of claim 1, wherein said substrate is p-doped and said p-epi layer comprises silicon, wherein said substrate is doped from 1×

10¹⁶ to 1×

10¹⁹ cm<sup>−

3</sup>, and wherein said p-epi layer is doped from 3×

10¹⁴ cm<sup>−

3</sup> to 3×

10¹⁶ cm<sup>−

3</sup>.

6. The ESD device of claim 1, wherein said ESD device includes at least one metal layer on a pre-metal dielectric (PMD), wherein said ground connection and said strike node connection are on-chip connections provided by said metal layer.

7. The ESD device of claim 4, wherein said ESD device is exclusive of any additional resistor in parallel to said resistance.

8. An integrated circuit (IC), comprising:

a substrate having a p-epitaxial (p-epi) layer thereon;

functional circuitry formed using said p-epi layer configured to realize and carry out a functionality having a plurality of terminals including at least a first terminal and a ground terminal;

at least one bipolar electrostatic discharge (ESD) protection device (ESD device) formed in said p-epi layer coupled between said first terminal and said ground terminal in parallel to said functional circuitry, said ESD device including;

a p-type epi region over an n-buried layer (NBL) formed in said p-epi layer thereon;

an n-type isolation tank (iso tank) comprising a deep n+ region (deep n+), said NBL containing a p-type isolated epi region of said epi region, and said iso tank having an n+ isolation contact;

an NPN transistor and an avalanche diode both formed in said isolated epi region;

said NPN transistor including an emitter within a base having a base contact and a collector comprising a top portion of said NBL;

said avalanche diode including a p-type anode region including an anode contact and an adjacent n-type cathode region having a cathode contact;

wherein said anode region and said base are resistively coupled together through said isolated epi region;

a ground connection coupling said emitter to said anode contact, and

a strike node connection coupling said cathode contact to said n+ isolation contact.

9. The IC of claim 8, further comprising an outer deep trench isolation ring (outer DT ring) framing said NPN transistor and said avalanche diode, and wherein said deep n+ is on a sidewall of a dielectric liner of said DT ring under a surface nwell region for connecting to said NBL.

10. The IC of claim 8, wherein said deep n+ comprises a vertically-diffused deep n+ region having a lateral diffusion of at least one micron.

11. The IC of claim 8, wherein said resistively coupled for said anode region and said base comprises a resistance of 30 ohms to 3,000 ohms.

12. The IC of claim 8, wherein said substrate is p-doped and said p-epi layer comprises silicon, wherein said substrate is doped from 1×

10¹⁶ to 1×

10¹⁹ cm<sup>−

3</sup>, and wherein said p-epi layer is doped from 3×

10¹⁴ cm<sup>−

3</sup> to 3×

10¹⁶ cm<sup>−

3</sup>.

13. The IC of claim 8, wherein said ESD device includes at least one metal layer metal 1 (M1) on a pre-metal dielectric (PMD), wherein said ground connection and said strike node connection are on-chip connections provided by said metal layer.

14. The IC of claim 11, wherein said ESD device is exclusive of any additional resistor in parallel to said resistance.

15. The IC of claim 8, wherein said IC comprises a Bipolar Metal Oxide Semiconductor (BiMOS) IC device.