Methods of fabricating semiconductor devices including multiple patterning

• US 9,461,058 B2
• Filed: 02/05/2016
• Issued: 10/04/2016
• Est. Priority Date: 02/09/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Song, Min-Sung, Sim, Jae-Hwang, Lim, Joon-Sung
• Primary Examiner(s): Blum, David S
• Application Number:
  US15/016,737
• Publication Number:
  US 20160233223A1
• Time in Patent Office: 242 Days
• Field of Search: 438/264
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0214 the material being a silicon oxynitride, e.g. SiON or SiON:H
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

Methods of fabricating semiconductor devices may include forming a stopper layer, a lower hard mask layer, an intermediate hard mask layer, and an upper hard mask pattern on a substrate, forming first spacer patterns on sidewalls of the upper hard mask pattern, selectively etching the intermediate hard mask layer using the first spacer patterns as an etching mask, forming second spacer patterns on sidewalls of the etched intermediate hard mask layer, selectively etching the lower hard mask layer using the etched second spacer layer as an etching mask, forming a patterning mask pattern that exposes a cell area and covers a common source line area on the etched lower hard mask layer and the stopper layer, and selectively etching the stopper layer using the etched lower hard mask layer and the patterning mask pattern as etching masks to form stopper patterns.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

forming a stopper layer, a lower hard mask layer, an intermediate hard mask layer, and an upper hard mask pattern on a substrate;

forming first spacer patterns on sidewalls of the upper hard mask pattern;

removing the upper hard mask pattern;

selectively etching the intermediate hard mask layer using the first spacer patterns as an etching mask to form intermediate hard mask patterns;

removing the first spacer patterns;

forming second spacer patterns on sidewalls of the intermediate hard mask patterns;

removing the intermediate hard mask patterns;

selectively etching the lower hard mask layer using the second spacer patterns as an etching mask to form lower hard mask patterns;

removing the second spacer patterns;

forming a patterning mask pattern that exposes a cell area and covers a common source line area on the lower hard mask patterns and the stopper layer;

selectively etching the stopper layer using the lower hard mask patterns and the patterning mask pattern as etching masks to form stopper patterns; and

removing the patterning mask pattern.

2. The method of claim 1, wherein the upper hard mask pattern comprises a first upper hard mask pattern and a second upper hard mask pattern disposed on the first upper hard mask pattern.

3. The method of claim 2, wherein the first upper hard mask pattern comprises a spin on hard mask (SOH) and the second upper hard mask pattern comprises silicon oxynitride.

4. The method of claim 1, wherein the intermediate hard mask layer comprises a first intermediate hard mask layer and a second intermediate hard mask layer disposed on the first intermediate hard mask layer.

5. The method of claim 4, wherein the first intermediate hard mask layer comprises a spin on hard mask (SOH) and the second intermediate hard mask layer comprises silicon oxynitride.

6. The method of claim 1, further comprising:

forming a tunnel dielectric layer and a data storage layer between the substrate and the stopper layer;

etching the tunnel dielectric layer and the data storage layer using the stopper patterns as an etching mask to form tunnel dielectric layer patterns and data storage layer patterns; and

etching the substrate using the stopper patterns as an etching mask to form cell trenches.

7. The method of claim 6, further comprising:

forming a core insulating layer on the substrate on which the cell trenches are formed;

recessing the core insulating layer to form a cell filling insulator in the cell trenches;

forming a dielectric layer on the cell filling insulator; and

forming a control gate electrode layer and a capping insulating layer on the dielectric layer.

8. The method of claim 1, wherein the patterning mask pattern comprises a photoresist.

9. The method of claim 1, wherein the patterning mask pattern comprises opening patterns that expose portions of the lower hard mask patterns and the stopper layer.

10. The method of claim 9,

wherein forming the stopper patterns comprises etching the stopper layer using the lower hard mask patterns that are exposed by the opening patterns as an etching mask to form the stopper patterns, and

wherein the lower hard mask patterns that are exposed by the opening patterns are not completely removed by etching the stopping layer.

11. The method of claim 9, wherein the opening patterns expose a “

U”

shape of the lower hard mask patterns in a plan view.

12. The method of claim 6, wherein ones of the cell trenches comprise an elongated rectangular shape in a plan view.

13. The method of claim 6, wherein ones of the cell trenches comprise a “

U”

shape in a plan view.

14. The method of claim 13, wherein forming the cell trenches comprises forming dummy areas in a shape that surrounds the cell trenches.

15. A method of fabricating a semiconductor device, the method comprising:

forming a stopper layer, a lower hard mask layer, an intermediate hard mask layer, and an upper hard mask layer on a substrate;

forming a first patterning mask pattern that has an elongated rectangular shape on the upper hard mask layer;

etching the upper hard mask layer using the first patterning mask pattern as an etching mask to form an upper hard mask pattern;

forming first spacer patterns on sidewalls of the upper hard mask pattern;

removing the upper hard mask pattern;

selectively etching the intermediate hard mask layer using the first spacer patterns as an etching mask to form intermediate hard mask patterns;

removing the first spacer patterns;

forming second spacer patterns on sidewalls of the intermediate hard mask patterns;

removing the intermediate hard mask patterns;

selectively etching the lower hard mask layer using the second spacer patterns as an etching mask to form lower hard mask patterns;

removing the second spacer patterns;

forming a second patterning mask pattern that exposes a cell area and covers a common source line area on the lower hard mask patterns and the stopper layer; and

selectively etching the stopper layer using the lower hard mask patterns and the second patterning mask pattern as etching masks to form stopper patterns.

16. A method of fabricating a semiconductor device, the method comprising:

forming an etch stop layer, a lower hard mask layer that has an etch selectivity with respect to the etch stop layer, a first intermediate hard mask layer that has an etch selectivity with respect to the lower hard mask layer, a second intermediate hard mask layer that has an etch selectivity with respect to the first intermediate hard mask layer, a first upper hard mask layer that has an etch selectivity with respect to the second intermediate hard mask layer, and a second upper hard mask layer that has an etch selectivity with respect to the first upper hard mask layer on a substrate;

forming a first patterning mask pattern on the second upper hard mask layer;

etching, in a first etch process, the first and second upper hard mask layers using the first patterning mask pattern as an etching mask to expose portions of the second intermediate hard mask layer;

removing the first patterning mask pattern;

forming a first spacer layer on portions of the first and second upper hard mask layers that remain after the first etch process and on the portions of the second intermediate hard mask layer that are exposed;

partially etching the first spacer layer and removing the second upper hard mask layer in a second etch process to expose the first upper hard mask layer and to form first spacer patterns on sidewalls of the first upper hard mask layer;

removing the first upper hard mask layer from between the first spacer patterns;

etching, in a third etch process, the first and second intermediate hard mask layers using the first spacer patterns as an etching mask to expose portions of the lower hard mask layer;

removing the first spacer patterns;

forming a second spacer layer on portions of the first and second intermediate hard mask layers that remain after the third etch process and on the portions of the lower hard mask layer that are exposed;

partially etching the second spacer layer and removing the second intermediate hard mask layer in a fourth etch process to expose the first intermediate hard mask layer and to form second spacer patterns on sidewalls of the first intermediate hard mask layer;

removing the first intermediate hard mask layer from between the second spacer patterns;

etching, in a fifth etch process, the lower hard mask layer using the second spacer patterns as an etching mask to expose portions of the etch stop layer; and

removing the second spacer patterns.

17. The method of claim 16, further comprising:

forming a tunnel dielectric layer and a data storage layer between the substrate and the etch stop layer;

forming a second patterning mask pattern comprising a plurality of openings spaced apart from each other and extending parallel to each other that expose portions of the lower hard mask layer that remain after the fifth etch process and portions of the etch stop layer;

etching, in a sixth etch process, the etch stop layer using the second patterning mask pattern and the portions of the lower hard mask layer that are exposed as etching masks; and

etching, in a seventh etch process, the data storage layer and the tunnel dielectric layer using portions of the etch stop layer remaining after the sixth etch process as an etching mask.

18. The method of claim 16, wherein the first patterning mask pattern comprises a plurality of parallel elongated rectangular shaped openings that expose portions of the second upper hard mask layer.

19. The method of claim 16, wherein the first patterning mask pattern comprises a plurality of parallel elongated rectangular shapes that cover portions of the second upper hard mask layer.

20. The method of claim 16, wherein spaces in a lateral direction between ones of the second spacer patterns are approximately equal to thicknesses in the lateral direction of the ones of the second spacer patterns.