Vertical power MOSFET having planar channel and its method of fabrication

• US 9,461,127 B2
• Filed: 10/01/2015
• Issued: 10/04/2016
• Est. Priority Date: 02/04/2014
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Zeng, Jun, Darwish, Mohamed N., Pu, Kui, Su, Shih-Tzung
• Primary Examiner(s): Schoenholtz, Joseph
• Application Number:
  US14/873,103
• Publication Number:
  US 20160027880A1
• Time in Patent Office: 369 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power MOSFET cell includes an N+ silicon substrate having a drain electrode. A low dopant concentration N-type drift layer is grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed and etched to have sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well'"'"'s lateral channel and has a vertical extension next to the top portion of the sidewalls. A positive gate voltage inverts the lateral channel and increases the conduction along the sidewalls to reduce on-resistance. A vertical shield field plate is also located next to the sidewalls and extends virtually the entire length of the sidewalls. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage.

Claims

1. A vertical transistor comprising

a semiconductor substrate having a first electrode on its bottom surface;

a first layer of a first conductivity type above the bottom surface of the substrate, the first layer having a first dopant concentration;

a second layer of the first conductivity type above the first layer, the second layer having a second dopant concentration higher than the first dopant concentration, the second layer having a top surface;

a trench having a vertical sidewall adjoining the second layer;

a well region of a second conductivity type in the top surface of the second layer, the well region having a top surface;

a first region of the first conductivity type in the top surface of the well region, wherein an area between the first region and an edge of the well region comprises a channel for inversion by a gate;

a conductive gate overlying the channel for creating a lateral conductive path in the channel when the gate is biased above a threshold voltage,

a vertical field plate facing the vertical sidewall of the second layer and insulated from the sidewall;

a second region of the first conductivity type surrounding and abutting the well region and extending to the trench vertical sidewall, the second region having a dopant concentration higher than the second dopant concentration for reducing on-resistance; and

a second electrode electrically contacting the well region and the first region, wherein when a voltage is applied between the first electrode and the second electrode and the gate is biased above the threshold voltage, a lateral current flows across the channel and a current flows between the channel and the substrate.

2. The transistor of claim 1 further comprising:

a third layer of the first conductivity type between the first layer and the second layer and located below the channel; and

a fourth layer of the second conductivity type laterally abutting the third layer on opposite sides of the third layer, a dopant concentration in the third layer and fourth layer being higher than the first dopant concentration.

3. The transistor of claim 2 further comprising a fifth layer of the second conductivity type below the trench and laterally adjacent to the second layer.

4. The transistor of claim 3 wherein the fifth layer abuts the fourth layer.

5. The transistor of claim 3 wherein the first layer is vertically separated from the fourth layer.

6. The transistor of claim 1 wherein the vertical field plate is electrically connected to the second electrode.

7. The transistor of claim 1 wherein the gate has a vertical extension facing the vertical sidewall and insulated from the sidewall, and wherein at least a portion of the vertical extension of the gate faces the second region.

8. The transistor of claim 1 wherein the vertical field plate is electrically connected to the gate.

9. The transistor of claim 1 wherein the vertical field plate is deeper than the well region.

10. The transistor of claim 1 wherein the gate has a vertical extension facing the vertical sidewall and insulated from the sidewall, and wherein the vertical extension of the gate extends below the well region.

11. The transistor of claim 1 wherein the well region extends to the vertical sidewall of the second layer.

12. The transistor of claim 11 wherein the gate has a vertical extension facing the vertical sidewall and insulated from the sidewall, and wherein the vertical extension of the gate inverts a portion of the well region abutting the vertical sidewall.

13. The transistor of claim 1 further comprising a third region of the second conductivity type below the trench and laterally adjacent to the second layer.

14. The transistor of claim 1 wherein the substrate is of the first conductivity type, and wherein the transistor is a MOSFET.

15. The transistor of claim 1 wherein the substrate is of the second conductivity type, and wherein the transistor is an IGBT.

16. The transistor of claim 1 wherein the vertical field plate and the second dopant concentration of the second layer are configured to enhance lateral depletion of the second layer so that the second layer is fully depleted at a breakdown voltage of the transistor.

17. The transistor of claim 1 further comprising:

a third layer of the first conductivity type between the first layer and the second layer and located below the channel; and

a fourth layer of the second conductivity type laterally abutting the third layer on opposite sides of the third layer, a dopant concentration in the third layer and fourth layer being higher than the first dopant concentration,

wherein the third layer and the fourth layer form N-type and P-type columns, where the N-type and P-type columns are fully depleted at a breakdown voltage of the transistor.

18. The transistor of claim 1 further comprising a third layer of the second conductivity type below the trench and laterally adjacent to the second layer.

19. The transistor of claim 1 further comprising:

a third region of the second conductivity type below the trench and laterally adjacent to the second layer; and

a fourth region of the second conductivity type along the vertical sidewall of the trench and running between the well region and the third region.

20. The transistor of claim 1 further comprising:

a third region of the second conductivity type below the trench and laterally adjacent to the second layer; and

a fourth region of the first conductivity type between the third region and the trench, and laterally adjacent to the second layer, wherein a dopant concentration in the fourth region is higher than the second dopant concentration of the second layer.

21. The transistor of claim 1 wherein first layer is formed as an epitaxial layer above the substrate.

22. A vertical transistor comprising

a semiconductor substrate having a first electrode on its bottom surface;

a first layer of a first conductivity type above the bottom surface of the substrate, the first layer having a first dopant concentration;

a second layer of the first conductivity type above the first layer, the second layer having a second dopant concentration higher than the first dopant concentration, the second layer having a top surface;

a trench having a vertical sidewall adjoining the second layer;

a well region of a second conductivity type in the top surface of the second layer, the well region having a top surface;

a first region of the first conductivity type in the top surface of the well region, wherein an area between the first region and an edge of the well region comprises a channel for inversion by a gate;

a conductive gate overlying the channel for creating a lateral conductive path in the channel when the gate is biased above a threshold voltage,

the gate having a vertical extension facing the vertical sidewall and insulated from the sidewall;

a vertical field plate facing the vertical sidewall of the second layer and insulated from the sidewall; and

a second electrode electrically contacting the well region and the first region, wherein when a voltage is applied between the first electrode and the second electrode and the gate is biased above the threshold voltage, a lateral current flows across the channel and a current flows between the channel and the substrate.

23. The transistor of claim 22 wherein the vertical field plate is electrically connected to the second electrode.

24. The transistor of claim 22 wherein the vertical field plate is electrically connected to the gate.

25. The transistor of claim 22 wherein the vertical field plate is deeper than the well region.

26. The transistor of claim 22 wherein the vertical extension of the gate extends below the well region.

27. The transistor of claim 22 wherein the vertical extension of the gate inverts a portion of the well region.

28. The transistor of claim 22 further comprising an enhanced doping region of the first conductivity type between the well region and the vertical sidewall for reducing on-resistance.

29. The transistor of claim 22 wherein the substrate is of the first conductivity type, and wherein the transistor is a MOSFET.

30. The transistor of claim 22 wherein the substrate is of the second conductivity type, and wherein the transistor is an IGBT.

31. The transistor of claim 22 wherein the vertical field plate and the second dopant concentration of the second layer are configured to enhance lateral depletion of the second layer so that the second layer is fully depleted at a breakdown voltage of the transistor.

32. The transistor of claim 22 wherein first layer is formed as an epitaxial layer above the substrate.