Semiconductor device manufacturing method including a counter layer for power conversion

• US 9,461,140 B2
• Filed: 06/11/2015
• Issued: 10/04/2016
• Est. Priority Date: 03/16/2011
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Onozawa, Yuichi, Shiigi, Takashi
• Primary Examiner(s): Nguyen, Thanh T
• Application Number:
  US14/736,532
• Publication Number:
  US 20150333146A1
• Time in Patent Office: 481 Days
• Field of Search: 438133-138
• US Class Current: 1/1
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 27/0664 Vertical bipolar transistor in combination with diodes
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/66325 controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]

Abstract

A p-type base layer is selectively formed on a surface of an n-type drift layer; an n-type source layer is selectively formed on a surface of the p-type base layer; and a p-type contact layer is formed to be in contact with the selectively-formed n-type source layer. A p-type counter layer is formed to be in contact with the n-type source layer, so as to overlap the p-type contact layer, so as to be separated from an interface where the p-type base layer and the gate oxide film are in contact with each other, and to be shallower than the p-type base layer. Accordingly, switching destruction caused by process defects in an insulated gate semiconductor device is reduced.

Claims

1. A method of manufacturing a semiconductor device comprising:

a first process of implanting second conductivity type impurity ions in a first principal plane of a semiconductor substrate with such a range that a contact layer is shallower than a base layer included in the semiconductor device in order to form the contact layer included in the semiconductor device;

a second process of implanting first conductivity type impurity ions in the first principal plane with such a range that a source layer is shallower than the contact layer in order to form the source layer included in the semiconductor device after the first process; and

a third process of implanting second conductivity type impurity ions in the first principal plane with such a range that a counter layer is deeper than the source layer and shallower than the base layer at a dose which is equal to or larger than 10% of a dose of the ion implantation of the first process in order to form the counter layer included in the semiconductor device after the second process, wherein the semiconductor device comprises;

a drift layer which includes a first conductivity type semiconductor substrate;

a second conductivity type base layer which is selectively formed on a surface of a first principal plane of the semiconductor substrate;

a first conductivity type source layer which is selectively formed on a surface of the base layer;

a second conductivity type contact layer which is formed to be in contact with the source layer on the first principal plane side of the base layer and which has a concentration higher than that of the base layer;

a gate electrode which is formed so as to face the drift layer, the base layer, and the source layer through an insulating film;

an emitter electrode which is formed on the first principal plane so as to be electrically connected to the source layer; and

an interlayer insulating film which is formed on the first principal plane of the semiconductor substrate to be interposed between the gate electrode and the emitter electrode so as to insulate the gate electrode and the emitter electrode,

wherein the semiconductor device further includes a second conductivity type counter layer which is formed to be in contact with the source layer and to overlap the contact layer and which is formed to be shallower than the base layer and to have a high concentration, and

wherein a total doping amount per unit area of the counter layer is larger than 10% of a total doping amount per unit area of the contact layer, and

wherein a sum of the total doping amount per unit area of the counter layer and the total doping amount per unit area of the contact layer is larger than that of the source layer.

2. The method according to claim 1, wherein the dose of ion implantation of the third process is larger than that of the first process.

3. The method according to claim 1, wherein a sum of the dose of ion implantation of the first process and the dose of ion implantation of the third process is larger than that of the second process.

4. The method according to claim 3, wherein the dose of ion implantation of the third process is larger than that of the second process.

5. The method according to claim 1, wherein the ion implantation of the third process is performed by using the interlayer insulating film, where an opening portion is selectively formed, as a mask.

6. The method according to claim 2, wherein a sum of the dose of ion implantation of the first process and the dose of ion implantation of the third process is larger than that of the second process.

7. The method according to claim 6, wherein the dose of ion implantation of the third process is larger than that of the second process.