Thyristor random access memory device and method

• US 9,461,155 B2
• Filed: 09/16/2013
• Issued: 10/04/2016
• Est. Priority Date: 06/29/2010
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tang, Sanh D., Zahurak, John K., Violette, Michael P.
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): Parker, John M
• Application Number:
  US14/028,242
• Publication Number:
  US 20140015001A1
• Time in Patent Office: 1,114 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/42308 Gate electrodes for thyristors
• CPC Class Codes: H01L 29/66363 Thyristors
• CPC Class Codes: H01L 29/74 Thyristor-type devices, e.g. having four-zone regenerative action two-terminal thyristors H01L29/87
• CPC Class Codes: H01L 2924/1301 Thyristor
• CPC Class Codes: H10B 99/20 comprising memory cells having thyristors

Abstract

Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided reduce a need for manufacturing methods such as deep dopant implants.

Claims

1. A thyristor memory device, comprising:

an array of memory cells, each memory cell including a folded first conductivity type region, each folded first conductivity type region having two upward facing ends;

a pair of second conductivity type semiconductor regions coupled to the upward facing ends;

a control line within the folded first conductivity type region between the two upward facing ends, and below the second conductivity type semiconductor regions;

a first conductivity type semiconductor cap on one of the second conductivity type semiconductor regions; and

a first transmission line coupled to the other second conductivity type semiconductor region.

2. The thyristor memory device of claim 1, wherein the first conductivity type is P-type and the second conductivity type is N-type.

3. The thyristor memory device of claim 1, further including a second transmission line coupled to the semiconductor cap.

4. The thyristor memory device of claim 3, wherein the second transmission line is substantially orthogonal to the first transmission line.

5. The thyristor memory device of claim 3, wherein the second transmission line includes a first conductivity type semiconductor material and a metal region.

6. The thyristor memory device of claim 1, wherein the first transmission line is shared between two adjacent memory cells in the array.

7. The thyristor memory device of claim 1, wherein the first transmission lines extend outwards to both sides of the array.

8. The thyristor memory device of claim 7, wherein the second transmission lines extend outwards to both sides of the array in an interleaved arrangement with the first transmission lines.