Semiconductor device including Schottky barrier diode and power MOSFETs and a manufacturing method of the same

• US 9,461,163 B2
• Filed: 09/17/2015
• Issued: 10/04/2016
• Est. Priority Date: 07/30/2004
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Shiraishi, Masaki, Uno, Tomoaki, Matsuura, Nobuyoshi
• Primary Examiner(s): Jahan, Bilkis
• Application Number:
  US14/857,596
• Publication Number:
  US 20160005854A1
• Time in Patent Office: 383 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/371 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/37124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/37147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/40095 Kinked
• CPC Class Codes: H01L 2224/40245 the item being metallic
• CPC Class Codes: H01L 2224/40247 Connecting the strap to a bond pad of the item
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48011 Length
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48095 Kinked
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48253 : connecting the wire to a potential ring of the item
• CPC Class Codes: H01L 2224/48624 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/4903 : Connectors having different sizes, e.g. different diameters
• CPC Class Codes: H01L 2224/49051 : Connectors having different shapes
• CPC Class Codes: H01L 2224/49111 : the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/49171 : Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 : Parallel arrangements
• CPC Class Codes: H01L 2224/73221 : Strap and wire connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/8385 : using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/84801 : Soldering or alloying
• CPC Class Codes: H01L 2224/8485 : using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/49524 : the additional leads being a tape carrier or flat leads
• CPC Class Codes: H01L 23/49562 : for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/37 : of an individual strap connector
• CPC Class Codes: H01L 24/40 : of an individual strap connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 27/0629 : in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/1095 : Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41741 : for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4232 : with insulated gate
• CPC Class Codes: H01L 29/4236 : within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 : characterised by the surface lay-out
• CPC Class Codes: H01L 29/45 : Ohmic electrodes
• CPC Class Codes: H01L 29/456 : on silicon
• CPC Class Codes: H01L 29/4916 : the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66143 : Schottky diodes
• CPC Class Codes: H01L 29/66734 : with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 : the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 : Schottky diodes
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01002 : Helium [He]
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01021 : Scandium [Sc]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/20753 : larger or equal to 30 microns less than 40 microns
• CPC Class Codes: H01L 2924/20755 : larger or equal to 50 microns less than 60 microns
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H02M 3/003 : Constructional details, e.g. physical layout, assembly, wiring or busbar connections
• CPC Class Codes: H02M 3/155 : using semiconductor devices only
• CPC Class Codes: H02M 7/003 : Constructional details, e.g. physical layout, assembly, wiring or busbar connections

Abstract

In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

Claims

1. A semiconductor device comprising:

a semiconductor chip including a schottky barrier diode and a plurality of power MOSFETs which are formed on a semiconductor substrate,

wherein the semiconductor substrate includes a first long side, a second long side located on the opposite side of the first long side, a first short side and a second short side located on the opposite side of the first short side,

wherein the schottky barrier diode is formed in a first region of the semiconductor substrate and includes an anode electrode and a cathode electrode,

wherein the plurality of power MOSFETs are formed in a plurality of second regions of the semiconductor substrate and respectively include a gate electrode, a source region and a drain region,

wherein a first metal layer is formed over the semiconductor substrate, is electrically connected to the gate electrodes and surrounds the first region and the second regions in a planar view,

wherein a plurality of gate fingers are unified with the first metal layer, are extending to a direction along the first short side and are arranged between each of the second regions,

wherein a second metal layer is formed over the first region and the second regions and is electrically connected to the source regions and the anode electrode, and

wherein a length along the first long side of the first region is larger than a length along the first short side of the first region.

2. A semiconductor device according to the claim 1,

wherein, in the direction along the first short side, the first region is arranged between the second regions arranged near the first long side and the second regions arranged near the second long side.

3. A semiconductor device according to the claim 1,

wherein each of the gate electrodes is formed in grooves formed in the semiconductor substrate.

4. A semiconductor device according to the claim 3,

wherein a length along the first long side of each of the gate electrodes is larger than a length along the first short side of each of the gate electrodes.

5. A semiconductor device according to the claim 1,

wherein each of the gate electrodes includes a poly silicon film,

wherein the first metal layer and gate fingers include a first aluminum film, respectively, and

wherein the second metal layer includes a second aluminum film.

6. A semiconductor device comprising:

a semiconductor chip including a schottky barrier diode and a plurality of power MOSFETs which are formed on a semiconductor substrate,

wherein the semiconductor substrate includes a first long side, a second long side located on the opposite side of the first long side, a first short side and a second short side located on the opposite side of the first short side,

wherein the schottky barrier diode is formed in a diode region of the semiconductor substrate and includes an anode electrode and a cathode electrode,

wherein the plurality of power MOSFETs are formed in first and second MOSFET regions of the semiconductor substrate and respectively include a gate electrode, a source region and a drain region,

wherein, in a direction along the first short side, the first MOSFET region, the diode region and the second MOSFET region are arranged in order,

wherein a first metal layer is formed over the semiconductor substrate, is electrically connected to the gate electrodes and surrounds the diode region, the first MOSFET region and the second MOSFET region in a planar view,

wherein a plurality of first gate fingers are unified with the first metal layer and are extending toward from the first long side to the second long side,

wherein a plurality of second gate fingers are unified with the first metal layer and are extending toward from the second long side to the first long side,

wherein the first MOSFET region is arranged between the first gate fingers,

wherein the second MOSFET region is arranged between the second gate fingers,

wherein a second metal layer is formed over the diode region, the first MOSFET region and the second MOSFET region and is electrically connected to the source regions and the anode electrode, and

wherein a length along the first long side of the diode region is larger than a length along the first short side of the diode region.

7. A semiconductor device according to the claim 6,

wherein each of the gate electrodes is formed in grooves formed in the semiconductor substrate.

8. A semiconductor device according to the claim 6,

wherein a length along the first long side of each of the gate electrodes is larger than a length along the first short side of each of the gate electrodes.

9. A semiconductor device according to the claim 8,

wherein each of the gate electrodes includes a poly silicon film,

wherein the first metal layer, the first gate fingers and the second gate fingers include a first aluminum film, respectively, and

wherein the second metal layer includes a second aluminum film.

10. A semiconductor device according to the claim 6,

wherein the power MISFETs are not formed in the diode region, and

wherein the schottky barrier diode is not formed in the first MOSFET region and the second MOSFET region.