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Device and method for fabricating thin semiconductor channel and buried strain memorization layer

  • US 9,461,169 B2
  • Filed: 05/28/2010
  • Issued: 10/04/2016
  • Est. Priority Date: 05/28/2010
  • Status: Active Grant
First Claim
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1. A method for inducing stress in a semiconductor layer, comprising:

  • forming a substrate structure, the substrate structure comprising a semiconductor base layer, a buried dielectric layer formed on the semiconductor base layer, and a semiconductor channel layer formed on the buried dielectric layer;

    ion implanting a dopant through an uppermost surface of the semiconductor channel layer and the buried dielectric layer into the semiconductor base layer to form an amorphized material region only in a portion of the semiconductor base layer that is in direct contact with the buried dielectric layer;

    depositing a stress layer after the amorphized region is formed, wherein the stress layer is directly on a surface of the semiconductor channel layer that is opposite a surface of the semiconductor channel layer that is in direct contact with the buried dielectric layer;

    annealing the substrate structure to memorize stress in a portion of the semiconductor base layer that is in direct contact with the buried dielectric layer by recrystallizing the amorphized material, wherein the memorized stress of the semiconductor base layer induces stress in the semiconductor channel layer;

    removing the stress layer; and

    forming a gate structure after removing the stress layer, wherein the gate structure is formed on the surface of the semiconductor channel layer that is opposite the surface of the semiconductor channel layer that is in direct contact with the buried dielectric layer, and wherein the gate structure includes an electrode layer and a gate dielectric layer that are separate layers from the substrate structure.

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