Power device and method for delivering power to electronic devices

• US 9,461,546 B2
• Filed: 01/30/2014
• Issued: 10/04/2016
• Est. Priority Date: 02/08/2013
• Status: Active Grant

• Current Assignee: Smart Prong Technologies, Inc.
• Original Assignee: Advanced Charging Technologies LLC
• Inventors: Freeman, Michael H., Weaver, W. J. Jim Jr., Freeman, Mitchael C., Dieter, Robert, Santee, Brian
• Primary Examiner(s): Dole, Timothy J
• Assistant Examiner(s): AHMED, YUSEF A
• Application Number:
  US14/168,364
• Publication Number:
  US 20150036389A1
• Time in Patent Office: 978 Days
• Field of Search: 363/16, 363/17, 363/20, 363/21.01, 363/21.02, 363/21.03, 363/62
• US Class Current: 1/1
• CPC Class Codes: H01R 31/065 with built-in electric apparatus
• CPC Class Codes: H02M 1/0009 Devices or circuits for detecting current in a converter
• CPC Class Codes: H02M 1/0032 Control circuits allowing low power mode operation, e.g. in standby mode
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 1/10 Arrangements incorporating converting means for enabling loads to be operated at will from different kinds of power supplies, e.g. from ac or dc
• CPC Class Codes: H02M 1/36 Means for starting or stopping converters
• CPC Class Codes: H02M 3/01 Resonant DC/DC converters
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H02M 3/335 using semiconductor devices only
• CPC Class Codes: H02M 3/33507 with automatic control of the output voltage or current, e.g. flyback converters H02M3/33561, H02M3/33569 take precedence
• CPC Class Codes: H02M 3/33592 having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
• CPC Class Codes: H02M 3/337 in push-pull configuration H02M3/33576 takes precedence; with self-oscillating arrangements H02M3/3382, H02M3/3385
• CPC Class Codes: H02M 3/3374 with preregulator, e.g. current injected push-pull
• CPC Class Codes: H02M 7/217 using semiconductor devices only
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

An energy efficient apparatus includes a switching device, a frequency dependent reactive device, and a control element is provided. The switching device is coupled to a source of electrical power and includes a pair of transistors and is adapted to receive a control signal and to produce an alternating current power signal. The frequency of the alternating current power signal is responsive to the control signal. The frequency dependent reactive device is electrically coupled to the pair of transistors for receiving the alternating current power signal and producing an output power signal. The frequency dependent reactive device is chosen to achieve a desired voltage of the output power signal relative to the frequency of the alternating current power signal. The control element senses an actual voltage of the direct current power signal and modifies the control signal delivered to achieve the desired voltage of the direct current power signal.

Claims

1. A voltage reduction apparatus for reducing a voltage level of a power signal received from a power source, comprising:

a voltage reduction circuit electrically coupled to the power source for receiving an input direct current (DC) input power signal having an input voltage level and discharging a DC output power signal having an output voltage level that is less than the input voltage level, the voltage reduction circuit including;

a plurality of switched capacitor devices for receiving the DC input power signal and discharging an intermediate DC power signal, each of the switched capacitor devices including a capacitor, an input switch, and a pair of output switches, each input switch of each of the switched capacitor devices configured to couple the switched capacitor devices in series with the source of electrical power for transmitting the DC input power signal from the source of electrical power to the capacitors of each of the switched capacitor devices, each pair of output switches of each of the switched capacitor devices configured to couple each of the switched capacitor devices in parallel to discharge the intermediate DC power signal from the plurality of switched capacitor devices; and

a buck converter coupled to the plurality of switched capacitor devices for receiving the intermediate DC power signal and delivering the DC output power signal to an electrical device;

a power circuit controller coupled to the plurality of switched capacitor devices and configured to;

detect the input power signal being received from the source of electrical power;

initiate a start-up routine including detecting a current draw of the electrical device upon detecting the input power signal;

initiate a sleep mode if the current draw of the electrical device is not detected including initiating a predefined sleep period and reinitiating the start-up routing upon expiration of the predefined sleep period;

initiate a charging routine if the current draw of the electrical device is detected, the charging routing including sensing the output voltage level and transmitting control signals to the switched capacitor device for regulating the switched capacitor device as a function of the sensed output voltage level; and

a vampire load elimination subsystem including a current sensor for sensing a current level of the DC output power signal, the vampire load elimination subsystem configured to shut-off input power to the voltage reduction circuit if the sensed current level is different from a predefined current level.

2. The voltage reduction apparatus in accordance with claim 1, wherein the plurality of switched capacitor devices includes a first switched capacitor device and a second switched capacitor device, the first switched capacitor device including a first capacitor and a first input switch coupled between the power source and the first capacitor, the second switched capacitor device including a second capacitor and a second input switch coupled between the first capacitor and the second capacitor.

3. The voltage reduction apparatus in accordance with claim 2, further comprising a semiconductor chip, the input and the output switching devices being formed on the semiconductor chip, the semiconductor chip including a substrate material including at least one of low Ohmic silicon, polysilicon, gallium nitride, gallium arsenide, silicon germanium, silicon carbide and indium phosphide.

4. The voltage reduction apparatus in accordance with claim 2, the switched capacitor device configured to operate between a charging state, a hold state, and a discharge state, the charging state including the input switching device in an on-position and the output switching devices in an off-position to transmit the DC input power signal to charge the capacitor, the hold state including each of the input switching device and the output switching devices in the off-position to isolate the capacitor, the discharging state including the input switching device in the off-position and the output switching devices in the on-position to discharge the capacitor.

5. The voltage reduction apparatus in accordance with claim 2, wherein each of the plurality of switched capacitor devices is operable between a charging state and a discharging state, the input switching devices configured to couple the capacitors in series in the charging state to transmit the DC input power signal to charge the capacitors, the output switching devices configured to couple the capacitors in parallel in the discharging state to discharge the intermediate DC power signal from the capacitors to the buck converter.

6. The voltage reduction apparatus in accordance with claim 5, the voltage reduction circuit including a hold capacitor electrically coupled to each of the switched capacitor devices, the plurality of switched capacitor devices being regulated to deliver the intermediate DC power signal to the hold capacitor in the discharge state.

7. The voltage reduction apparatus in accordance with claim 1, the voltage reduction circuit including a transformer, a primary side of the transformer being coupled to the buck converter for receiving a DC power signal from the buck converter and generating the DC output power signal.

8. The voltage reduction apparatus in accordance with claim 1, further comprising a rectifier circuit coupled between the power source and the voltage reduction circuit for receiving an alternating current (AC) power signal from the power source and transmitting resulting DC power signal to the voltage reduction circuit.