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Programmable logic circuit architecture using resistive memory elements

  • US 9,461,649 B2
  • Filed: 06/03/2013
  • Issued: 10/04/2016
  • Est. Priority Date: 06/01/2012
  • Status: Active Grant
First Claim
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1. An electronic device having a programmable logic circuit architecture, comprising:

  • a field-programmable gate array (FPGA) comprised of one or more logic blocks (LBs) that provide customizable logic functions, wherein the logic blocks are connected to routing channels through one or more connection blocks (CBs) and the routing channels are connected with each other through one or more switching blocks (SBs);

    wherein the connection blocks, routing channels, and switching blocks comprise programmable interconnects that are programmed using one or more resistive memory elements, the resistive memory elements are arranged in the same layer, and the programmable interconnects are fabricated over the logic blocks.

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