Programmable logic circuit architecture using resistive memory elements

• US 9,461,649 B2
• Filed: 06/03/2013
• Issued: 10/04/2016
• Est. Priority Date: 06/01/2012
• Status: Active Grant

• Current Assignee: Regents of the University of California (University of California)
• Original Assignee: Regents of the University of California (University of California)
• Inventors: Cong, Jingsheng J., Xiao, Bingjun
• Primary Examiner(s): Hammond, Crystal L
• Application Number:
  US14/404,874
• Publication Number:
  US 20150123706A1
• Time in Patent Office: 1,219 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H03K 19/1736 in which the wiring can be modified
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices

Abstract

A programmable logic circuit architecture using resistive memory elements. The proposed circuit architecture uses the conventional island-based Field Programmable Gate Array (FPGA) architecture, but with novel integration of CMOS-compatible resistive memory elements that can be programmed efficiently. In the proposed architecture, the programmable interconnects of FPGA are redesigned to use only resistive memory elements and metal wires. Then, the interconnects can be entirely fabricated over logic blocks to save area while keeping their architectural functions unchanged, and the programming transistors can be shared among resistive memory elements to save area. Finally, on-demand buffer insertion is proposed as the buffering solution to achieve more speedup.

Claims

1. An electronic device having a programmable logic circuit architecture, comprising:

a field-programmable gate array (FPGA) comprised of one or more logic blocks (LBs) that provide customizable logic functions, wherein the logic blocks are connected to routing channels through one or more connection blocks (CBs) and the routing channels are connected with each other through one or more switching blocks (SBs);

wherein the connection blocks, routing channels, and switching blocks comprise programmable interconnects that are programmed using one or more resistive memory elements, the resistive memory elements are arranged in the same layer, and the programmable interconnects are fabricated over the logic blocks.

2. The device of claim 1, wherein the resistive memory elements comprise resistive random access memories (RRAM) or memristors.

3. The device of claim 1, wherein the resistive memory elements are CMOS-compatible resistive memory elements.

4. The device of claim 1, wherein the resistive memory elements are programmed using programming transistors that are shared among the resistive memory elements in the programmable interconnects.

5. The device of claim 1, wherein the programmable interconnects are fabricated in a layer different from the logic blocks, and the field-programmable gate array has an area that is defined by the logic blocks only.

6. The device of claim 1, wherein the field-programmable gate array includes on-demand buffer insertion in the programmable interconnects.

7. The device of claim 6, wherein positions of inserted buffers for the on-demand buffer insertion are optimized according to a design of the field-programmable gate array.

8. The device of claim 1, wherein the programmable interconnects are built up from only the resistive memory elements and metal wires, but no transistors.

9. A method for fabricating an electronic device having a programmable logic circuit architecture, comprising:

fabricating a field-programmable gate array (FPGA) comprised of one or more logic blocks (LBs) that provide customizable logic functions, wherein the logic blocks are connected to routing channels through one or more connection blocks (CBs) and the routing channels are connected with each other through one or more switching blocks (SBs);

wherein the connection blocks, routing channels, and switching blocks comprise programmable interconnects that are programmed using one or more resistive memory elements, the resistive memory elements are arranged in the same layer, and the programmable interconnects are fabricated over the logic blocks.

10. The method of claim 9, wherein the resistive memory elements comprise resistive random access memories (RRAM) or memristors.

11. The method of claim 9, wherein the resistive memory elements are CMOS-compatible resistive memory elements.

12. The method of claim 9, wherein the resistive memory elements are programmed using programming transistors that are shared among the resistive memory elements in the programmable interconnects.

13. The method of claim 9, wherein the programmable interconnects are fabricated in a layer different from the logic blocks, and the field-programmable gate array has an area that is defined by the logic blocks only.

14. The method of claim 9, wherein the field-programmable gate array includes on-demand buffer insertion in the programmable interconnects.

15. The method of claim 14, wherein positions of inserted buffers for the on-demand buffer insertion are optimized according to a design of the field-programmable gate array.

16. The method of claim 9, wherein the programmable interconnects are built up from only the resistive memory elements and metal wires, but no transistors.